Dual-edge fifo interface

Abstract

A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

We claim:  
     
       1. A dual-edge FIFO interface, comprising: 
       a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full;  
       a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full; and  
       a register block in communication with the host FIFO and the target FIFO;  
       wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.  
     
     
       2. A dual-edge FIFO interface as in  claim 1 , wherein the interface is configurable as a synchronous FIFO by removing or bypassing synchronization. 
     
     
       3. A dual-edge FIFO interface as in  claim 1 , wherein the interface is configurable as an asynchronous FIFO using synchronization signals. 
     
     
       4. A dual edge FIFO interface as in  claim 1 , wherein the interface is configurable with different combination RAM or block register size. 
     
     
       5. A dual edge FIFO interface as in  claim 1 , wherein the interface is configurable to receive and/or transmit data at different data rates. 
     
     
       6. A dual edge FIFO interface as in  claim 1 , wherein the interface is further operative to receive data on both edges of the host clock.