Solid-state electronic image sensing device and method of controlling operation of same

Abstract

Subsampling of data is performed at a high subsampling rate in an image sensing device such as a CCD. Signal lines for applying transfer pulses to transfer gates in the device are connected so as to apply gate pulses simultaneously to transfer gates for photodiodes of (n+1)th, (n+5)th and (n+13)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of an (n+2)th row, apply gate pulses simultaneously to transfer gates for photodiodes of (n+3)th, (n+7)th, (n+11)th and (n+15)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+4)th, (n+8)th, (n+12)th and (n+16)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+6)th, (n+10)th and (n+14)th rows, and apply gate pulses simultaneously to transfer gates for photodiodes of an (n+9)th row.

What is claimed is:  
     
       1. A solid-state electronic image sensing device having: 
       a number of photodiodes formed in row and column directions;  
       vertical transfer paths formed adjacent to photodiodes in the row direction and in which vertical transfer electrodes have been formed; and  
       transfer gates for transferring signal charge, which has accumulated in said photodiodes, to said vertical transfer paths;  
       wherein signal lines for applying gate pulses to said transfer gates are connected so as to apply gate pulses simultaneously to transfer gates for photodiodes of (n+1)th, (n+5)th and (n+13)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of an (n+2)th row, apply gate pulses simultaneously to transfer gates for photodiodes of (n+3)th, (n+7)th, (n+11)th and (n+15)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+4)th, (n+8)th, (n+12)th and (n+16)th rows, apply gate pulses simultaneously to transfer gates for photodiodes of (n+6)th, (n+10)th and (n+14)th rows, and apply gate pulses simultaneously to transfer gates for photodiodes of an (n+9)th row.  
     
     
       2. The device according to  claim 1 , further comprising a first gate-pulse output device for applying gate pulses in such a manner that application of gate pulses to transfer gates for photodiodes of odd-numbered rows is performed in a field different from that in which application of gate pulses to transfer gates for photodiodes of even-numbered rows is performed. 
     
     
       3. The device according to  claim 1 , further comprising a second gate-pulse output device for applying gate pulses simultaneously to transfer gates for photodiodes in two rows among (m+1)th, (m+2)th, (m+3)th and (m+4)th rows in odd-numbered fields and applying gate pulses simultaneously to transfer gates for photodiodes of (m+1)th, (m+2)th, (m+3)th and (m+4)th rows in even-numbered fields with the exception of those transfer gates of rows to which gate pulses were applied in the odd-numbered fields. 
     
     
       4. The device according to  claim 1 , further comprising a third gate-pulse output device for applying gate pulses simultaneously to transfer gates for photodiodes in one or two rows among (m+1)th, (m+2)th, (m+3)th and (m+4)th rows. 
     
     
       5. The device according to  claim 1 , further comprising a fourth gate-pulse output device for applying gate pulses simultaneously to transfer gates for photodiodes in (n+2)th and (n+9)th rows. 
     
     
       6. A method of controlling the operation of a solid-state electronic image sensing device having a number of photodiodes formed in row and column directions, vertical transfer paths formed adjacent to photodiodes in the row direction and in which vertical transfer electrodes have been formed, and transfer gates for transferring signal charge, which has accumulated in said photodiodes, to said vertical transfer paths, said method comprising the steps of: 
       applying gate pulses simultaneously to transfer gates for photodiodes of (n+1)th, (n+5)th and (n+13)th rows;  
       applying gate pulses simultaneously to transfer gates for photodiodes of an (n+2)th row;  
       applying gate pulses simultaneously to transfer gates for photodiodes of (n+3)th, (n+7)th, (n+11)th and (n+15)th rows;  
       applying gate pulses simultaneously to transfer gates for photodiodes of (n+4)th, (n+8)th, (n+12)th and (n+16)th rows;  
       applying gate pulses simultaneously to transfer gates for photodiodes of (n+6)th, (n+10)th and (n+14)th rows; and  
       applying gate pulses simultaneously to transfer gates for photodiodes of an (n+9)th row.