Synchronous semiconductor memory device having a burst mode for improving efficiency of using the data bus

Abstract

A semiconductor memory device has a mask signal receiving circuit which receives a data mask signal, fed from an external unit, out of synchronism and produces an asynchronous internal mask signal. The semiconductor memory device includes a function for interrupting a reading of data during a burst output in response to the data mask signal. The reading of data during the burst output is interrupted by using the internal mask signal. Therefore, the operation time can be shortened when the burst reading is interrupted by a write processing, and thereby the efficiency for using the data bus can be enhanced and the operation can be executed at higher speeds.

What is claimed is:  
     
       1. A semiconductor memory device having a function for interrupting a reading of data during a burst output in response to a data mask signal fed from a external unit, comprising: 
       a mask signal receiving circuit receiving said data mask signal out of synchronism with an internal clock signal and producing an asynchronous internal mask signal;  
       wherein the reading of data during said burst output is interrupted by using said internal mask signal.  
     
     
       2. The semiconductor memory device as claimed in  claim 1 , further comprising a data output circuit producing read data in synchronism with a clock signal, and an output control circuit producing an output control signal upon receiving said internal mask signal and masking the output data from said data output circuit. 
     
     
       3. The semiconductor memory device as claimed in  claim 2 , wherein said mask signal receiving circuit comprises: 
       a switch circuit interrupting a reception of said data mask signal for only a first period in synchronism with said clock signal; and  
       a latch circuit holding a state of before being interrupted;  
       wherein said data output circuit masks the output data upon receiving said output control signal during said first period.  
     
     
       4. The semiconductor memory device as claimed in  claim 3 , wherein said first period is set to a delay time shorter than a time for holding said data mask signal for said clock signal. 
     
     
       5. The semiconductor memory device as claimed in  claim 4 , wherein said mask signal receiving circuit has a first operation mode and a second operation mode, the first operation mode being a mode for receiving said data mask signal out of synchronism, and said second operation mode being a mode for receiving said data mask signal in synchronism with said clock signal. 
     
     
       6. The semiconductor memory device as claimed in  claim 5 , further comprising a register in which said first operation mode and said second operation mode are set. 
     
     
       7. The semiconductor memory device as claimed in  claim 6 , wherein an operation mode of said mask signal receiving circuit is generated based upon a latency data set to said register. 
     
     
       8. The semiconductor memory device as claimed in  claim 2 , wherein said data output circuit produces an output of a high-impedance state in response to said output control signal, and masks said output data.