Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor

Abstract

A low-power bipolar transistor is formed to have a silicon germanium base region, an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The silicon germanium base region increases the speed of the transistor, while the small extrinsic emitter region reduces the maximum current that can flow through the transistor, and the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.

What is claimed is:  
     
       1. A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of: 
       forming a layer of first isolation material on the epitaxial layer;  
       forming a layer of second isolation material on the layer of first isolation material;  
       etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;  
       forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer;  
       planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material.  
     
     
       2. The method of  claim 1  wherein the planarizing step removes the layer of second isolation material from the layer of first isolation material. 
     
     
       3. The method of  claim 2  wherein an area and location of a base-to-collector junction is defined by an area and location of the portion of the layer of second isolation material. 
     
     
       4. The method of  claim 1  wherein the layer of conductive material is formed by a blanket deposition. 
     
     
       5. A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of: 
       forming a layer of first isolation material on the epitaxial layer;  
       forming a layer of second isolation material on the layer of first isolation material;  
       etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;  
       forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer, the layer of first conductive material being silicon germanium, and the layer of first conductive material has a second conductivity type; and  
       planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material, the planarizing removing the layer of second isolation material from the layer of first isolation material.  
     
     
       6. A method for forming a bipolar transistor on a wafer, the wafer having a buried layer, an epitaxial layer of a first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of: 
       forming a layer of first isolation material on the epitaxial layer;  
       forming a layer of second isolation material on the layer of first isolation material;  
       etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to form an exposed region of the epitaxial layer;  
       forming a layer of first conductive material on the layers of first and second isolation materials and the exposed region of the epitaxial layer;  
       planarizing the layer of first conductive material to form an intrinsic base region surrounded by the layer of first isolation material;  
       forming an isolation region on the intrinsic base region;  
       forming a layer of second conductive material on the isolation region and the intrinsic base region;  
       etching the layer of second conductive material to form an extrinsic emitter on the isolation region and the intrinsic base region;  
       etching the isolation region such that a side wall of the extrinsic emitter and a side wall of the isolation region are substantially aligned;  
       forming a side-wall spacer on the intrinsic base region to adjoin the extrinsic emitter;  
       forming an extrinsic base region in the intrinsic base region after the side-wall spacer has been formed; and  
       forming an intrinsic emitter region in the intrinsic base region after the extrinsic base region has been formed.  
     
     
       7. The method of  claim 6  wherein the step of forming the isolation region on the intrinsic base region includes the steps of: 
       forming a layer of third isolation material on the intrinsic base region; and  
       etching the layer of third isolation material to form the isolation region.  
     
     
       8. The method of  claim 6  and further comprising the step of planarizing the layer of second conductive material prior to the step of etching the layer of second conductive material. 
     
     
       9. The method of  claim 6  wherein the step of etching the layer of second conductive material is a timed etch. 
     
     
       10. The method of  claim 6  wherein the extrinsic emitter has an end that contacts the intrinsic base region. 
     
     
       11. The method of  claim 10  wherein the end has a substantially vertical end wall, the end wall lying in a plane that is unparallel with a plane that includes substantially all of the side wall of the extrinsic emitter. 
     
     
       12. The method of  claim 6  wherein a top surface area of the extrinsic emitter is less than a top surface area of the isolation region. 
     
     
       13. The method of  claim 12  wherein a width of the extrinsic emitter is less than a width of the isolation region, the width of the extrinsic emitter and the width of the isolation region being measured along a line substantially perpendicular to a plane that includes substantially all of the side wall of the extrinsic emitter. 
     
     
       14. The method of  claim 6  wherein the step of etching the isolation region is a wet etch with an etchant that etches more oxide than silicon. 
     
     
       15. The method of  claim 6  wherein the layer of second conductive material is polysilicon. 
     
     
       16. The method of  claim 15  wherein the layer of second conductive material is doped to have the first conductivity type. 
     
     
       17. The method of  claim 6  wherein the step of forming an intrinsic emitter region includes the step of annealing the wafer to cause dopants to outdiffuse from the extrinsic emitter into the intrinsic base region. 
     
     
       18. The method of  claim 6  wherein a top surface of the extrinsic emitter substantially lies in a plane, and a portion of the side-wall spacer lies in the plane. 
     
     
       19. The method of  claim 6  and further comprising the step of forming a base silicide layer on the intrinsic base region and an emitter suicide layer on the extrinsic emitter. 
     
     
       20. The method of  claim 19  wherein the step of forming the base silicide layer includes the steps of: 
       depositing a layer of metal on the extrinsic emitter, the side-wall spacer, and the intrinsic base region; and  
       heating the layer of metal to form the base silicide layer and the emitter silicide layer.  
     
     
       21. A method of forming a bipolar transistor on a wafer, the wafer having a buried layer of a first conductivity type, and an intermediate layer of the first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of: 
       forming a layer of first isolation material on the intermediate layer;  
       forming a layer of second isolation material on the layer of first isolation material;  
       etching a portion of the layer of second isolation material and an underlying portion of the layer of first isolation material to expose a surface region of the intermediate layer;  
       forming a layer of first conductive material on the surface region of the intermediate layer;  
       planarizing the layer of first conductive material to form a conductive region surrounded by the layer of first isolation material;  
       forming an isolation region on the conductive region;  
       forming a layer of second conductive material on the isolation region and the conductive region; and  
       etching the layer of second conductive material to form an emitter on the isolation region and the conductive region, and expose the conductive region.  
     
     
       22. The method of  claim 21  wherein the planarizing step removes the layer of second isolation material from the layer of first isolation material. 
     
     
       23. The method of  claim 22   
       wherein the emitter has a first surface that contacts the isolation region and a second surface that contacts the conductive region, the first surface having a first area and lying in a first plane, the second surface having a second area and lying in a second plane substantially parallel with the first plane, the first area being substantially greater than the second area.  
     
     
       24. A method of forming a bipolar transistor on a wafer, the wafer having a buried layer of a first conductivity type, and an intermediate layer of the first conductivity type formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of: 
       forming a conductive region on the intermediate layer;  
       forming an isolation region on the conductive region;  
       forming a layer of conductive material on the isolation region and the conductive region; and  
       etching the layer of conductive material to form an emitter on the isolation region and the conductive region, and expose the conductive region.  
     
     
       25. The method of  claim 24  wherein the emitter includes: 
       a first surface that contacts the isolation region, the first surface lying in a first plane;  
       a second surface that contacts the conductive region, the second surface lying in a second plane that is substantially parallel to the first plane, the second surface being smaller than the first surface.  
     
     
       26. The method of  claim 25  wherein the conductive region has a second conductivity type. 
     
     
       27. The method of  claim 26   
       wherein the emitter further includes a third surface that contacts the second surface, the third surface lying in a third plane that is substantially perpendicular to the first and second planes; and  
       further comprising the step of forming an isolating side wall spacer on the conductive region, the isolating side wall spacer contacting the third surface of the emitter.  
     
     
       28. The method of  claim 27  and further comprising the step of annealing to cause dopant atoms to outdiffuse from the emitter into the conductive region to form an intrinsic emitter region. 
     
     
       29. The method of  claim 27  and further comprising the step of implanting dopant atoms of the second conductivity type into the conductive region after the isolating side wall spacers have been formed to form an extrinsic base region in the conductive region. 
     
     
       30. The method of  claim 26  wherein the conductive region includes silicon germanium.