Efficient fabrication process for dual well type structures

Abstract

An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
       1. A method of masking a semiconductor substrate to form high and low voltage devices comprising: 
       applying a first mask over a first surface of said substrate, said mask including a first aperture;  
       doping a first region of said substrate through said first aperture;  
       removing said first mask from over said first surface;  
       applying a second mask over said first surface, said second mask including a second aperture;  
       doping a second region of said substrate through said second aperture, said first and second regions being non-intersecting regions;  
       redoping said second region of said substrate through said second aperture;  
       removing said second mask from over said first surface;  
       applying a third mask over said first surface, said third mask including third and fourth apertures, said third aperture being disposed over said first region and said fourth aperture being disposed over said second region;  
       doping a portion of said first region aligned with said third aperture and doping a portion of said second region aligned with said fourth aperture;  
       removing said third mask from over said first surface;  
       forming first and second electronic devices in said first and second regions respectively; and  
       forming a third electronic device in said portion of said second region aligned with said fourth aperture.  
     
     
       2. A method as defined in  claim 1  further comprising: 
       thermally processing said substrate after said doping said first region and prior to said doping said second region to form a diffusion well within said first region.  
     
     
       3. A method as defined in  claim 1  wherein said doping of said first region includes implanting ions into said first region at an energy of approximately 200 keV. 
     
     
       4. A method as defined in  claim 1  wherein said doping of said second region includes implanting ions into said second region at an energy of greater than approximately 240 keV to form a retrograde well within said second region. 
     
     
       5. A method of processing a semiconductor substrate with three masks to form plural differentiated transistor gate regions comprising: 
       forming a first mask on a first surface of said substrate, said first mask including a first opening exposing a first area of said first surface for a diffusion well;  
       implanting a first plurality of ions into said substrate through said first opening;  
       removing said first mask from said first surface of said substrate;  
       heating said substrate to diffuse said first plurality of ions within said substrate;  
       forming an isolation region on said substrate at said first surface;  
       growing an oxide layer over said substrate above said first surface;  
       forming a second mask on said oxide layer above said first surface of said substrate including a second opening exposing a second area of said oxide layer for a retrograde well;  
       implanting a second plurality of ions into said substrate through said second opening to form said retrograde well;  
       doping said substrate within said retrograde well through said second opening  
       removing said second mask;  
       forming a third mask having a plurality of further openings therein on said oxide layer above said first surface, one of said further openings being disposed above said first area and another of said further openings being disposed above said second area;  
       stripping said oxide layer within said plurality of further openings; and  
       doping said substrate through said plurality of further openings to form said plural differentiated transistor gate regions.  
     
     
       6. A method of processing a semiconductor substrate as defined in  claim 5  wherein said doping said substrate within said retrograde well includes excessive doping of said substrate. 
     
     
       7. A sequence of three semiconductor manufacturing masks comprising: 
       a first mask, including a first opening, adapted to be deposited on a first surface of a semiconductor substrate, said first opening adapted to expose a first area of said semiconductor substrate to a first source of implantation ions;  
       a second mask, including a second opening, adapted to be deposited above said first surface of said semiconductor substrate, said second opening adapted to expose a second area of said semiconductor substrate to a second source of implantation ions, said second opening further adapted to expose said second area to a first source of doping ion; and  
       a third mask, including third and fourth openings, adapted to be deposited above said first surface of said semiconductor substrate, said third and fourth openings adapted to expose respective portions of said first and second areas to a second source of doping ions, said first second and third mask adapted to be applied to said semiconductor substrate sequentially.  
     
     
       8. A method of forming a solid state device comprising: 
       masking a semiconductor substrate in a first pattern defining a first well area and exposing said semiconductor substrate to a first source of a first plurality of ions;  
       thereafter, de-masking said semiconductor substrate and heating said semiconductor substrate to diffuse said first plurality of ions within said first well area;  
       thereafter, forming an isolation region on said thereafter substrate;  
       thereafter, growing an oxide layer over said semiconductor substrate;  
       thereafter, re-masking said semiconductor substrate and said oxide layer in a second pattern defining a second well area and exposing said semiconductor substrate to a second source of a second plurality of ions;  
       thereafter, exposing said semiconductor substrate to a third source of doping ions;  
       thereafter, de-masking said semiconductor substrate;  
       thereafter, re-masking said semiconductor substrate in a third pattern defining first and second regions including said first and second well areas respectively;  
       thereafter, stripping said two respective portions of said oxide within said first and second regions respectively; and  
       exposing said semiconductor substrate to a fourth source of doping ions so as to dope said substrate within said first and second regions respectively.