Video signal processing system for driving multiple monitors

Abstract

Disclosed is a video signal processing system for outputting video signals for driving monitors during one period of clock signal. The system includes: a clock signal (CLK) supply part for outputting CLK for transmitting video signal; a monitor controller for outputting memory access signal (MA) by the period of CLK; a memory buffer for outputting data signal according to MA; latch circuits for latching data signal, dividing into multiple data during one period of CLK and outputting the latched data to the monitors; an inverter inverting CLK; a delay circuit delaying inverted CLK; and a flip-flop circuit for outputting in flip-flop after receiving delayed CLK and inputting into the latch circuits.

What is claimed is:  
     
       1. A video signal processing system for driving multiple monitors, the system comprising: 
       a clock signal supply part for outputting a first clock signal (CLK) for transmitting video signal;  
       a monitor controlling part for outputting a memory access signal (MA) according to a period of the first CLK provided from the CLK supply part;  
       a memory for outputting a data signal according to the MA output from the monitor controlling part after receiving the MA output from the monitor controlling part and receiving video signal (R/G/B) and horizontal/vertical sync signal (H/V-sync) from a video card through a single cable;  
       a plurality of latch circuits for latching the data signal output from the memory, dividing into multiple data during one period of the first CLK and outputting the latched data to the monitors;  
       an inverter for inverting the first CLK output from the CLK supply part and outputting a second CLK;  
       a delay circuit for delaying the second CLK inverted by the inverter and outputting a third CLK; and  
       a flip-flop circuit for outputting in flip-flop after receiving the third CLK from the delay circuit and inputting into the latch circuits.  
     
     
       2. The system according to  claim 1 , wherein the CLK supply part is a central processing unit (CPU) for providing video clock. 
     
     
       3. The system according to  claim 1 , wherein the delay circuit delays signal during a low level period of CLK inverted by the inverter. 
     
     
       4. The system according to  claim 1 , wherein the flip-flop circuit is a D type flip-flop circuit outputting Q and {overscore (Q)} signals. 
     
     
       5. The system according to  claim 1 , wherein the latch circuits have the same number as the monitors to be driven. 
     
     
       6. The system according to  claim 1 , wherein the memory is a RAM buffer. 
     
     
       7. The system according to  claim 1 , wherein data signal of relatively shorter period of data signals divided by the latch circuits is used for driving a relatively small-sized monitor, and data signal of relatively longer period is used for driving a relatively large-sized monitor. 
     
     
       8. The system according to  claim 1 , wherein the delay circuit divides and outputs into long/short data signals by delaying and outputting half period of signal from one period of signal. 
     
     
       9. The system according to one of claims  3 ,  7  and  8 , wherein delay time during a low level period delayed by the delay circuit is equal with the period of data signal having the long period. 
     
     
       10. The system according to  claim 1 , wherein one flip-flop circuit is connected with two latch circuits.