Structures to mechanically stabilize isolated top-level metal lines

Abstract

The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization layer formed upon the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one signal line coupled to the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one protective structure that surrounds the signal line.

What is claimed is:  
     
       1. An integrated circuit comprising: 
       a first interconnection metallization layer formed upon a substrate; and  
       a second interconnection metallization layer formed upon the first interconnection metallization layer, the second interconnection metallization layer having formed therein at least one signal line coupled to the first interconnection metallization layer;  
       wherein the second interconnection metallization layer has formed therein a plurality of protective structures (PSi) for i=. . . N, a first protective structure PS 1  surrounding the at least one signal line, each protective structure PSi surrounding a previous protective structure PSi- 1 .  
     
     
       2. The integrated circuit of  claim 1 , wherein one of the at least one protective structure is coupled to a low rail supply voltage. 
     
     
       3. The integrated circuit of  claim 1 , wherein one of the at least one protective structure is coupled to a high rail supply voltage. 
     
     
       4. The integrated circuit of  claim 1 , wherein the at least one protective structure has a continuous loop shape that encloses the signal line. 
     
     
       5. The integrated circuit of  claim 1 , wherein the at least one protective structure is spaced from the signal line at approximately 2 microns. 
     
     
       6. The integrated circuit of  claim 1 , wherein the first interconnection metallization layer has a first volume and the second interconnection metallization layer has a second volume greater than the first volume.