Semiconductor device

Abstract

A DMOS transistor in which a main current flows between first and second main surfaces of a silicon substrate is formed. DMOS transistor has a p-type diffusion region formed in the first main surface, an n+ diffusion region formed in the first main surface in p-type diffusion region, and a gate electrode facing p-type diffusion region sandwiched between n+ diffusion region and n- layer via a gate insulating layer. A dielectric layer is formed in the silicon substrate so as to be adjacent to n- layer, and made of a material having a dielectric constant higher than that of silicon. Therefore, the semiconductor device which can be easily formed while suppressing increase in process cost and has an improved trade-off (effective on-state resistance) between a withstand voltage and on-state resistance by generating an electric field almost uniform in the direction of the thickness of a semiconductor substrate can be attained.

What is claimed is:  
     
       1. A semiconductor device comprising: 
       a silicon substrate of a first conduction type having first and second main surfaces facing each other; and  
       an insulated gate type field effect transistor in which a main current flows between said first main surface and said second main surface,  
       said insulated gate type field effect transistor comprising:  
       a first impurity region of a second conduction type formed in said first main surface;  
       a second impurity region of the first conduction type formed in said first impurity region;  
       a first conduction type region in said silicon substrate extending between said first and second main surfaces, wherein said first impurity region is sandwiched between said first conduction type region and said second impurity region;  
       a gate electrode layer facing said first impurity region with a gate insulating layer interposed therebetween; and  
       a dielectric layer extending between said first and second main surfaces formed in said silicon substrate so as to be adjacent to said first conduction type region in said silicon substrate and made of a material having a dielectric constant higher than that of silicon.  
     
     
       2. The semiconductor device according to  claim 1 , wherein said dielectric layer is constructed so that the dielectric constant decreases with distance from said first main surface side toward said second main surface side. 
     
     
       3. The semiconductor device according to  claim 1 , wherein said dielectric layer is formed at said second main surface side immediately below said gate electrode layer. 
     
     
       4. The semiconductor device according to  claim 1 , further comprising a third impurity region of the second conduction type formed between said dielectric layer and said first conduction type region in said silicon substrate. 
     
     
       5. The semiconductor device according to  claim 1 , wherein said dielectric layer becomes wider and said first conduction type region in said silicon substrate becomes narrower with distance from said first main surface side toward said second main surface side.