US6598291B2ExpiredUtilityA1
Via connector and method of making same
Est. expiryMar 20, 2018(expired)· nominal 20-yr term from priority
H05K 1/113H05K 3/426H05K 3/246H05K 2201/0959H05K 3/4069H05K 2201/0347Y10T29/49128H01R 12/523H05K 2201/0355Y10T29/49165Y10T29/49155H05K 3/0094H05K 2203/1461
71
PatentIndex Score
17
Cited by
43
References
28
Claims
Abstract
An insulator substrate or printed circuit board (PCB) having a filled and plated via. A sidewall of the via and preferably opposite sides of the insulator substrate are first plated with a conductive material. The plated via is then filled with an electrically conductive fill composition. A conductive cap layer is preferably formed over both ends of the conductive fill composition and the opposite surfaces of the insulator substrate, and can be bonded to a surface mount contact as a land or a pad.
Claims
exact text as granted — not AI-modifiedWhat is claimed:
1. A method of preparing a printed circuit board (PCB), comprising the steps of:
forming a hole in a substrate to form a via having a sidewall extending therethrough;
depositing a first conductive material on opposite sides of the substrate and on the sidewall of the via;
filling the via with a second conductive material to plug the via such that the via has no opening extending completely therethrough in a direction generally perpendicular to the opposite sides of the substrate, wherein the second conductive material is a conductive ink; and
depositing a third conductive material on the first conductive material and on ends of the second conductive material in the via.
2. The method according to claim 1 , wherein the step of forming the hole comprises one of drilling the hole, punching the hole, laser drilling the hole, and forming the hole by photo-definition.
3. The method according to claim 1 , wherein the first conductive material comprises copper.
4. The method according to claim 3 , wherein the step of depositing the first conductive material includes electrolytically depositing the first conductive material to a substantially uniform thickness of greater than approximately 0.2 mils.
5. The method according to claim 4 , wherein the substantially uniform thickness is approximately 0.5 mils.
6. The method according to claim 1 , further comprising the step of masking the substrate with a stencil to permit selective filling of the via prior to the step of filling the via.
7. The method according to claim 1 , further comprising the step of curing the conductive ink prior to the step of depositing the third conductive material.
8. The method according to claim 7 , further comprising the step of removing any of the conductive ink extending out of the via prior to the step of depositing the third conductive material.
9. The method according to claim 1 , wherein the conductive ink comprises at least one of silver, copper, and a noble metal.
10. The method according to claim 1 , wherein the step of depositing the third conductive material comprises one of feature plating and panel plating, and the third conductive material comprises copper.
11. The method according to claim 10 , wherein the step of depositing the third conductive material includes depositing the third conductive material to a substantially uniform thickness of between about 0.4 mils and about 0.8 mils.
12. The method according to claim 11 , wherein the substantially uniform thickness is approximately 0.5 mils.
13. The method according to claim 1 , further comprising the step of depositing a fourth conductive material on the opposite sides of the substrate and on the sidewall of the via prior to the step of depositing the first conductive material.
14. The method according to claim 13 , wherein the fourth conductive material comprises one of palladium and platinum.
15. The method according to claim 13 , wherein the step of depositing the fourth conductive material includes depositing the fourth conductive material to a substantially uniform thickness of between about 30 micro-inches and about 200 micro-inches.
16. The method according to claim 15 , wherein the substantially uniform thickness is between about 70 micro-inches and about 80 micro-inches.
17. The method according to claim 1 , wherein the substrate comprises a resin material.
18. The method according to claim 17 , wherein the resin material is a glass-filled resin material.
19. The method according to claim 1 , further comprising the step of etching the first and third conductive materials so as to form wiring patterns on the opposite sides of the substrate.
20. A method of making a conductive via in an insulator circuit board substrate adapted to carry wiring patterns on an at least a first surface and a second surface thereof, comprising the steps of:
providing an insulator substrate;
forming a via having a sidewall in the insulator substrate between the first surface and the second surface by penetrating the insulator substrate;
depositing a first conductive layer on the first surface and on the sidewall of the via such that the first conductive layer substantially covers the first surface of the insulator substrate and the sidewall of the via while leaving an opening in the via;
depositing a conductive material in the opening of the via to plug the via such that the opening does not extend completely through the via in a direction generally perpendicular to the first and second surfaces, wherein the conductive material is a conductive ink; and
forming a second conductive layer on the first surface of the insulator substrate subsequent to the forming of the via, the depositing of the first conductive layer, and the depositing of the conductive material in the opening such that the second conductive layer forms a substantially flat surface extending across substantially all of the first conductive layer and across an end portion of the conductive material in the via so that the end portion is covered by and makes direct contact with the second conductive layer.
21. The method according to claim 20 , further comprising the step of etching the first and second conductive layers so as to form a wiring pattern on the first surface of the insulator substrate, the wiring pattern being electrically connected through the via to the second surface.
22. The method according to claim 20 , further comprising the step of masking the insulator substrate with a stencil to permit selective filling of the opening prior to the step of depositing the conductive material in the opening, wherein the conductive material is deposited so as to completely fill the opening.
23. The method according to claim 20 , wherein the step of depositing the second conductive layer comprises one of feature plating and panel plating and the first and second conductive layers comprise copper.
24. The method according to claim 20 , wherein the insulator substrate comprises a glass-filled resin material.
25. A method of preparing a printed circuit board (PCB), comprising the steps of:
forming a hole on at least one side of a substrate to form a via extending at least partially through the substrate to an internal surface of the substrate, the via having a sidewall;
depositing a first conductive material on said one side of the substrate and on the sidewall of the via such that the via has an opening;
masking the substrate with a stencil;
filling the opening with a second conductive material by moving the second conductive material through an opening in the stencil to plug the via such that the opening in the via does not extend completely through the via in a direction generally perpendicular to said one side of the substrate, wherein the second conductive material is a conductive ink; and
depositing a third conductive material on the first conductive material and on an end of the second conductive material in the opening.
26. The method according to claim 25 , wherein the step of depositing the first conductive material comprises electrolytically plating copper to a substantially uniform thickness exceeding approximately 0.2 mils.
27. A method of preparing a printed circuit board (PCB), comprising the steps of:
forming a plurality of holes on at least a first surface of a substrate to forma plurality of vias extending at least partially through the substrate to a second surface of the substrate, the vias having sidewalls;
depositing a first conductive material on at least the first surface of the substrate and on the sidewalls of the vias such that each of the vias has an associated opening;
masking the substrate with a stencil to selectively cover a first predetermined number of the vias and reveal a second predetermined number of the vias;
filling the openings associated with the revealed vias with a second conductive material, wherein the second conductive material is a conductive ink; and
depositing a third conductive material on the first conductive material and on ends of the second conductive material in the filled openings.
28. The method according to claim 27 , wherein the step of depositing the first conductive material comprises electrolytically plating copper to a substantially uniform thickness exceeding approximately 0.2 mils.Join the waitlist — get patent alerts
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