Method and apparatus for electro-static discharge protection

Abstract

A circuit includes an output driver, where the output driver includes a pull-up device and a pull-down device. The pull-up device has a first control terminal that is responsive to an RC-timer so as to bias the pull-up device on in response to an electrostatic discharge (ESD) event that activates a device coupled to an output of the RC-timer. The pull-down device has a second control terminal that, for one aspect, is in a substantially indeterminate state (i.e. the second control terminal may be a “1”, “0” or some other voltage, which may or may not be within the voltage range between “1” and “0”) during the ESD event.

What is claimed is:  
     
       1. A circuit comprising: 
       an output driver including a pull-up device and a pull-down device;  
       said pull-up device comprising a first control terminal responsive to an RC-timer to bias said pull-up device on in response to an electrostatic discharge (ESD) event that causes a device coupled to an output of said RC-timer to be activated; and  
       said pull-down device comprising a second control terminal, said second control terminal being coupled in said circuit so as to be in a substantially indeterminate state in response to said ESD event,  
       wherein said RC-timer comprises a resistor-capacitor (RC) network, a first inverting stage and a second inverting stage; wherein said RC network is coupled with an input terminal of said first inverting stage; and an output terminal of said first inverting stage is coupled with an input terminal of said second inverting stage.  
     
     
       2. The circuit of  claim 1 , wherein an output terminal of said second inverting stage is coupled with a control terminal of said device that is an ESD clamping device. 
     
     
       3. The circuit of  claim 2  wherein said ESD clamping device comprises a p-channel transistor and said control terminal of said ESD clamping device comprises a gate terminal of said p-channel transistor. 
     
     
       4. The circuit of  claim 1 , wherein said first control terminal is coupled with said output terminal of said first inverting stage via a NOR gate, wherein said output terminal of said first inverting stage is coupled with a first input terminal of said NOR gate, logic circuitry for controlling said pull-up device during normal operation of the output driver is coupled with a second input terminal of said NOR gate, and an output terminal of said NOR gate is coupled with said first control terminal. 
     
     
       5. The circuit of  claim 4 , wherein said NOR gate comprises a two-input NOR gate. 
     
     
       6. A circuit comprising: 
       an output driver, wherein said output driver comprises a pull-up device and a pull-down device;  
       said pull-up device comprising a first control terminal responsive to an RC-timer to bias said pull-up device on in response to an electrostatic discharge (ESD) event that activates a device coupled to an output of said RC-timer; and  
       said pull-down device comprising a second control terminal coupled in said circuit such that, in response to said ESD event, said second control terminal is to be biased at a voltage that is between a power supply voltage and a ground voltage for said circuit.  
     
     
       7. The circuit of  claim 6 , wherein said pull-up device comprises a p-channel transistor and said pull-down device comprises an n-channel transistor. 
     
     
       8. The circuit of  claim 7 , wherein said RC-timer comprises a resistor-capacitor (RC) network, a first inverting stage and a second inverting stage; wherein said RC network is coupled with an input terminal of said first inverting stage; and an output terminal of said first inverting stage is coupled with an input terminal of said second inverting stage. 
     
     
       9. The circuit of  claim 8 , wherein an output terminal of said second inverting stage is coupled with a control terminal of said device that is an ESD clamping device, said ESD clamping device comprising a p-channel transistor and said control terminal of said ESD clamping device comprising a gate terminal of said p-channel transistor. 
     
     
       10. The circuit of  claim 6 , wherein said second control terminal is responsive to an electronic signal from said RC-timer to be biased at said voltage between said power supply voltage and said ground voltage. 
     
     
       11. The circuit of  claim 10 , further comprising a voltage divider to generate said voltage between said power supply voltage and said ground voltage, said voltage divider being coupled with said RC-timer and said pull-down device. 
     
     
       12. The circuit of  claim 11 , wherein said voltage divider comprises a plurality of p-channel transistors, said p-channel transistors being coupled in series between a power supply terminal and a ground supply terminal, via their source and drain terminals, and coupled with said RC-timer via their gate terminals, so as to be biased on in response to said ESD event; and 
       wherein said second control terminal is coupled with a source terminal of one of said plurality of p-channel transistors and a drain terminal of another of said plurality of p-channel transistors.  
     
     
       13. The circuit of  claim 12 , wherein said plurality of p-channel transistors comprises two p-channel transistors, said two p-channel transistors having substantially equal channel resistances. 
     
     
       14. A method comprising: 
       detecting an electrostatic discharge (ESD) event that activates a device coupled to an output of an RC-timer;  
       turning on a pull-up device of an output driver in response to activating said device; and  
       applying a voltage to a control terminal of a pull-down device of said output driver during said ESD event, said voltage being a substantially constant fraction of a voltage differential between a power supply voltage and a ground supply voltage.  
     
     
       15. The method of  claim 14 , wherein applying said voltage includes receiving said voltage from a voltage divider. 
     
     
       16. The method of  claim 14 , wherein applying said voltage includes applying a voltage of substantially zero volts. 
     
     
       17. The method of  claim 14 , wherein applying a said voltage includes applying a voltage that is substantially equal to one half of a value of said voltage differential.