MOS transistor

Abstract

Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a source/drain region and a channel stop region under a field oxide film are obtained, and the drain withstand voltage can be controlled. Low impurity concentration source and drain regions of a second conductivity type are formed in a semiconductor substrate surrounded by a field oxide film and a gate electrode. An interlayer insulating film is formed thereover for electrically insulating a gate electrode and the source and drain regions. A wiring layer is formed on the interlayer insulating film. A pair of contact holes are formed to extend through the interlayer insulating film to expose a portion of the source and drain regions for electrically connecting the wiring layer, the gate electrode, and the source and drain regions, and high impurity concentration diffusion layers of the second conductivity type are formed only in the exposed portion of each of the source and drain regions.

What is claimed is:  
     
       1. A semiconductor device having one or more MOS transistors, each MOS transistor comprising: 
       a field oxide film formed on a semiconductor substrate having a first conductivity type;  
       a channel stop region having the first conductivity type formed in the semiconductor substrate under the field oxide film;  
       a gate insulating film formed on the semiconductor substrate;  
       a gate electrode formed on the gate insulating film  
       low impurity concentration source and drain regions of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate surrounded by the field oxide film and the gate electrode;  
       an interlayer insulating film for electrically insulating the gate electrode and the source and drain regions;  
       a wiring layer formed on the interlayer insulating film;  
       a pair of contact holes extending through the interlayer insulating film to expose a portion of the source and drain regions for electrically connecting the wiring layer, the gate electrode, and the source and drain regions; and  
       a high impurity concentration diffusion layer of the second conductivity type formed only in the exposed portion of each of the source and drain regions.  
     
     
       2. A semiconductor device according to  claim 1 ; wherein an impurity concentration of the low impurity concentration source and drain regions is in the range of 1E16 to 1E18 atoms/cm 3 . 
     
     
       3. A semiconductor device according to  claim 1 ; wherein an impurity concentration of the high impurity concentration diffusion layer is in the range of 1E19 to 5E20 atoms/cm 3 . 
     
     
       4. A semiconductor device according to  claim 1 ; wherein a plurality of the MOS transistors are formed on the semiconductor substrate each having a different withstand voltage, the different withstand voltages being set by varying a width of the source and drain regions by changing a distance between one end of the gate electrode and one end of each diffusion layer. 
     
     
       5. A semiconductor device according to  claim 1 ; wherein the low impurity concentration source and drain regions are formed by ion-implanting impurities into the surface of the semiconductor substrate using the gate electrode as a mask; and the high concentration diffusion layers are formed by ion-implanting impurities into the surface of the semiconductor substrate using the contact hole as a mask. 
     
     
       6. A semiconductor device according to  claim 1 ; wherein the interlayer insulating film is a BPSG film. 
     
     
       7. A semiconductor device having one or more MOS transistors, each comprising: 
       a field oxide film formed on a semiconductor substrate having a first conductivity type;  
       a channel stop region having the first conductivity type formed in the semiconductor substrate under the field oxide film;  
       a gate insulating film formed on the semiconductor substrate;  
       a gate electrode formed on the gate insulating film;  
       a channel region formed under the gate electrode;  
       low impurity concentration source and drain regions of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate surrounded by the field oxide film and the gate electrode;  
       an interlayer insulating film for electrically insulating the gate electrode and the source and drain regions;  
       a wiring layer formed on the interlayer insulating film;  
       a pair of contact holes extending through the interlayer insulating film for electrically connecting the wiring layer, the gate electrode, and the source and drain regions; and  
       high impurity concentration source and drain regions having an impurity concentration within the range of 1E19 to 5E20 atoms/cm 3  of the second conductivity type formed under the contact holes and separated from the channel region and the channel stop region;  
       wherein the high and low impurity concentration source and drain regions are formed with regions in which impurities are implanted and regions in which no impurities are implanted so that impurity concentration profiles thereof may be varied by varying a relationship between the regions in which the impurities are implanted and the regions in which no impurities are implanted.  
     
     
       8. A semiconductor device according to  claim 7 ; wherein an impurity concentration of the low impurity concentration source and drain regions is in the range of 1E16 to 5E20 atoms/cm 3 . 
     
     
       9. A semiconductor device according to  claim 7 ; wherein the regions where impurities are implanted and the regions where impurities are not implanted are formed in a dot shape. 
     
     
       10. A semiconductor device according to  claim 7 ; wherein the regions where impurities are implanted and the regions where impurities are not implanted are formed in a grid shape. 
     
     
       11. A semiconductor device according to  claim 7 ; wherein the regions where impurities are implanted and the regions where impurities are not implanted are formed in a stripe shape. 
     
     
       12. A semiconductor device according to  claim 7 ; wherein the regions where impurities are implanted and the regions where impurities are not implanted are formed by implanting ions into the surface of the semiconductor substrate by using a patterned photoresist mask, followed by conducting a heat treatment, to thereby simultaneously form at least two regions of different impurity concentrations. 
     
     
       13. A semiconductor device according to  claim 12 ; wherein the interlayer insulating film is a BPSG film. 
     
     
       14. A MOS transistor comprising: a semiconductor substrate having a first conductivity type; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; low impurity concentration source and drain regions of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate adjacent the gate electrode; an interlayer insulating film for electrically insulating the gate electrode and the source and drain regions; a wiring layer formed on the interlayer insulating film; contact holes extending through the interlayer insulating film to expose a portion of the source and drain regions for electrically connecting the wiring layer, the gate electrode, and the source and drain regions; and high impurity concentration diffusion regions having an impurity concentration of the second conductivity type formed only in the exposed portion of each of the source and drain regions. 
     
     
       15. A MOS transistor according to  claim 14 ; further comprising a field oxide film formed on the semiconductor substrate. 
     
     
       16. A MOS transistor according to  claim 15 ; further comprising a channel stop region formed in the semiconductor substrate under the field oxide film. 
     
     
       17. A MOS transistor according to  claim 14 ; wherein an impurity concentration of the low impurity concentration source and drain regions is in the range of 1E16 to 1E18 atoms/cm 3 . 
     
     
       18. A MOS transistor according to  claim 14 ; wherein an impurity concentration of the high impurity concentration diffusion layer is in the range of 1E19 to 5E20 atoms/cm 3 . 
     
     
       19. A MOS transistor according to  claim 18 ; wherein the interlayer insulating film is a BPSG film. 
     
     
       20. A MOS transistor according to  claim 14 ; wherein the low impurity concentration source and drain regions comprise a plurality of regions having different impurity concentrations so that concentration profile of the source and drain regions may be arbitrarily varied by changing a relationship between the regions having different impurity concentrations.