Integrated circuit layout system, integrated circuit layout method, and computer-readable storage medium storing program therefor

Abstract

A dummy gate processing unit obtains a netlist and generates a dummy-gate-inserted netlist (step S 13 ). In accordance with the netlist stored in a netlist storing unit, a floor plan processing unit makes module divisions and performs grouping (step S 16 ). Besides, the floor plan processing unit distributes dummy gates to the individual target modules divided, and then makes area divisions in the respective target modules (step S 18 ). A layout processing unit determines such coordinates that the dummy gates are arranged uniformly within the respective divided areas (step S 22 ), arranges all cells, and install all net wiring (step S 25 ).

What is claimed is:  
     
       1. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to modules of the integrated circuit in accordance with said netlist, said netlist having dummy gate information inserted therein by said dummy gate inserting unit; and  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within areas on a chip corresponding to said modules.  
     
     
       2. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       an area designating unit for designating a plurality of areas on a chip to arrange said circuit elements in accordance with said netlist;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to said plurality of areas; and  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within said respective areas on the chip.  
     
     
       3. An integrated circuit layout method comprising: 
       inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       distributing a predetermined number of dummy gates to modules of the integrated circuit in accordance with said netlist having dummy gate information inserted therein; and  
       arranging said predetermined number of dummy gates so that the dummy gates are distributed uniformly within said respective modules corresponding to areas on a chip.  
     
     
       4. An integrated circuit layout method comprising: 
       inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       designating a plurality of areas on a chip to arrange circuit elements in accordance with said netlist having dummy gate information inserted therein;  
       distributing a predetermined number of dummy gates to said areas; and  
       arranging said predetermined number of dummy gates uniformly within said respective areas on the chip.  
     
     
       5. A computer-readable storage medium storing a program for causing a computer to perform an integrated circuit layout process comprising: 
       inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       distributing a predetermined number of dummy gates to modules of the integrated circuit in accordance with said netlist having dummy gate information inserted therein; and  
       arranging said predetermined number of dummy gates uniformly within said respective modules corresponding to areas on a chip.  
     
     
       6. A computer-readable storage medium storing a program for causing a computer to perform an integrated circuit layout process comprising: 
       inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       designating a plurality of areas on a chip to arrange said circuit elements in accordance with said netlist having dummy gate information inserted therein;  
       distributing a predetermined number of dummy gates to said areas; and  
       arranging said predetermined number of dummy gates uniformly within said respective areas on the chip.  
     
     
       7. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to modules in accordance with said netlist having dummy gate information inserted therein by said dummy gate inserting unit;  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within respective modules corresponding to areas on a chip; and  
       wherein said dummy gate information includes at least a total number of dummy gates which are inserted into a top level of the netlist, wherein the netlist is hierarchical; and  
       wherein said dummy gate distributing unit distributes said predetermined number of dummy gates included in said dummy gate information in accordance with a number of circuit elements targeted for the distribution.  
     
     
       8. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       an area designating unit for designating a plurality of areas on a chip to arrange said circuit elements in accordance with said netlist having dummy gate information inserted therein by said dummy gate inserting unit;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to said plurality of areas;  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within said respective areas on the chip; and  
       wherein said dummy gate information includes at least a total number of dummy gates which are inserted into a top level of the netlist, wherein the netlist is hierarchical; and  
       wherein said dummy gate distributing unit distributes said predetermined number of dummy gates in accordance with a number of circuit elements targeted for the distribution.  
     
     
       9. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to modules in accordance with said netlist having dummy gate information inserted therein by said dummy gate inserting unit;  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within respective modules corresponding to areas on a chip; and  
       wherein one or more of said predetermined number of dummy gates is used to redesign said connections of said integrated circuit.  
     
     
       10. An integrated circuit layout system comprising: 
       a dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit;  
       an area designating unit for designating a plurality of areas on a chip to arrange circuit elements in accordance with said netlist having dummy gate information inserted therein by said dummy gate inserting unit;  
       a dummy gate distributing unit for distributing a predetermined number of dummy gates to said areas;  
       a dummy gate arranging unit for arranging said predetermined number of dummy gates uniformly within said respective areas on the chip; and  
       wherein one or more of said predetermined number of dummy gates is used to redesign said connections of said integrated circuit.