Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit

Abstract

A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

What is claimed is:  
     
       1. A circuit for selectively enabling one among a plurality of circuit paths in an integrated circuit, comprising: 
       selection circuit means for selecting one among the circuit paths, the selection circuit means having first and second control inputs;  
       at least one latch that controls the selections means, each of said at last one latch having a tendency to switch to a preferred state, the at least one latch comprising:  
       a first circuit branch comprising a first transistor and a second transistor serially connected between the supply voltage and ground  
       a second circuit branch comprising a third transistor and a fourth transistor serially connected between the supply voltage and ground;  
       a first common node between the first and the second transistor connected to control electrodes of the third and fourth transistor and to the first control input of the selection circuit means;  
       a second common node between the third and fourth transistor connected to control electrodes of the first and second transistor and to the second control input of the selection circuit means, the third and fourth transistors having turn-on voltages respectively lower, in absolute value, than the turn-on voltages of the first and second transistors;  
       at least one metal electrical interconnection line connecting the first common node of a respective one of the at least one latch to ground to force the at least one latch into a state opposite the preferred state, the at least one latch automatically switching to the preferred state when the at least one metal electrical interconnection line is interrupted;  
       a first capacitor coupled between the first common node and the power supply line; and  
       a second capacitor coupled between the second common node and the ground line.  
     
     
       2. The circuit of  claim 1 , wherein the first, second, third, and fourth transistors are field-effect transistors.