Reduction of induced charge in SOI devices during focused ion beam processing

Abstract

A method of substantially reducing charge build-up in a SOI device is provided. The method includes depositing a dielectric material on a surface of a semiconductor structure which includes at least silicon-on-insulator (SOI) devices therein. Next, a first conductive material is deposited on the dielectric material and then holes are drilled through the conductive material and the dielectric insulating material. Each hole is filled with a second conductive material, and thereafter selective portions of the first conductive material are removed to form contact pads for further probing. The method is especially useful in focused ion beam (FIB) drilling.

What is claimed is:  
     
       1. A method of substantially reducing charge build-up in SOI devices comprising the steps of: (a) depositing a dielectric material on a surface of a semiconductor structure, said structure including at least silicon-on-insulator (SOI) devices; (b) depositing a first conductive material on said dielectric material; (c) drilling holes through said first conductive material and said dielectric material; (d) filling said holes with a second conductive material; and (e) selectively removing portions of said first conductive material, stopping on said dielectric material. 
     
     
       2. The method of  claim 1  wherein said semiconductor structure further includes a semiconductor chip having one or more interconnect levels formed thereon. 
     
     
       3. The method of  claim 2  wherein said interconnect levels include at least wiring regions. 
     
     
       4. The method of  claim 1  wherein said dielectric material is an insulating material selected from the group consisting of oxides, nitrides, oxynitrides, polyamides, parylene polymers, polystyrene, Si-containing polymers, aromatic thermosetting polymeric resins and mixtures and/or multilayers thereof. 
     
     
       5. The method of  claim 4  wherein said dielectric material is an oxide. 
     
     
       6. The method of  claim 1  wherein said dielectric material is deposited by chemical vapor deposition (CVD), plasma-assisted CVD, evaporation, sputtering, chemical solution deposition or atomic layer deposition. 
     
     
       7. The method of  claim 1  wherein said first conductive material is composed of Al, Cu, W, Ti, Au, Pt, Pd or alloys and/or multilayers thereof. 
     
     
       8. The method of  claim 7  wherein said first conductive material is composed of Al or Cu. 
     
     
       9. The method of  claim 1  wherein said first conductive material is deposited by CVD, plasma-assisted CVD, evaporation, sputtering or plating. 
     
     
       10. The method of  claim 1  wherein said drilling step includes focus ion beam drilling, laser beam drilling or bit drilling. 
     
     
       11. The method of  claim 10  wherein said drilling step comprises focus ion beam drilling. 
     
     
       12. The method of  claim 1  wherein said first conductive material is connected to a ground potential during said drilling step. 
     
     
       13. The method of  claim 1  wherein said drilling step is used in conjunction with an alignment process. 
     
     
       14. The method of  claim 1  wherein a dry etching process precedes said drilling step to enlarge said holes. 
     
     
       15. The method of  claim 14  wherein said dry etching process comprises reactive-ion etching, ion beam etching, or plasma etching. 
     
     
       16. The method of  claim 1  wherein said holes expose wiring regions present in the underlying semiconductor structure. 
     
     
       17. The method of  claim 1  wherein said filling step includes CVD, plasma-assisted CVD, sputtering, plating or evaporation. 
     
     
       18. The method of  claim 1  wherein said second conductive material comprises Al, Cu, W, Ti, Au, Pt, Pd or alloys thereof. 
     
     
       19. The method of  claim 1  wherein step (e) comprises focus ion beam etching, lithography and etching, or laser etching.