Semiconductor chip packaging method

Abstract

A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating material on the first surface; etching the conductive layer from a second surface of the wafer and depositing a conductive track extending from a contact of the second chip surface to the exposed surface of the conductive area; covering the second surface with a second thick plate forming a rigid cap; and etching the first plate above the conductive layer to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.

What is claimed is:  
     
       1. A method for packaging a chip formed in a semiconductor wafer and having electric contacts on both its surfaces, including the steps of: 
       providing, on a first surface of the wafer, at least one conductive area extending beyond the periphery of the chip to be formed;  
       gluing a first thick plate including an electrically isolating material on the first surface;  
       etching the wafer from its second surface to define chips;  
       depositing at least one conductive track extending from a contact of the second chip surface to the conductive area;  
       covering the second surface with a second thick plate forming a rigid cap with an interposed isolating filling material between the first and second plates; and  
       etching the first plate at least above the at least one conductive area to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.  
     
     
       2. The method of  claim 1 , further including a final cutting step to separate the packages. 
     
     
       3. The method of  claim 1 , wherein the first isolating plate is thinned before being opened above the conductive area. 
     
     
       4. The method of  claim 1 , wherein the second surface of the wafer is thinned before the step of chip definition etching. 
     
     
       5. The method of  claim 1 , wherein the thickness of the second covering plate is chosen according to the desired mechanical bond of the package once completed. 
     
     
       6. The method of  claim 1 , wherein the etching of the first thick plate is performed according to a pattern of formation of two pads per chip. 
     
     
       7. The method of  claim 6 , wherein a contact transfer from the conductive area is performed in an separation area of the two pads, to the exposed surface of one of the pads. 
     
     
       8. The method of  claim 1 , wherein the second plate is made of an electrically isolating material. 
     
     
       9. The method of  claim 1 , wherein the second plate is, at least partially, made of a thermally conductive material. 
     
     
       10. A method for packaging a chip formed in a semiconductor wafer and having electric contacts on both its surfaces, including the steps of: 
       providing, on a first surface of the wafer, at least one conductive area extending beyond the periphery of the chip to be formed; and  
       applying a first plate on the first surface; and  
       etching the wafer from a second surface of the wafer to define a chip; and  
       depositing at least one conductive layer extending from a contact of the second surface to the at least one conductive area; and  
       covering the second surface with a second plate; and  
       etching the first plate at least above the at least one conductive area to provide at least a first etched portion; and  
       depositing a conductive material over the first etched portion and extending to a first surface of the first plate outside the first etched portion, wherein the conductive material forms a first conductance path from the at least one conductive area to the first surface of the first plate.  
     
     
       11. The method of  claim 10 , wherein the first plate includes an electrically isolating material. 
     
     
       12. The method of  claim 11 , wherein the step of applying the first plate includes gluing the first plate to the first surface. 
     
     
       13. The method of  claim 10 , further comprising the step of interposing isolating filling material between the first and second plates. 
     
     
       14. The method of  claim 10 , wherein the second plate forms a rigid cap over the entire second surface. 
     
     
       15. The method of  claim 10 , wherein the etching the first plate includes etching over a second contact region of the first surface to form a second etched portion. 
     
     
       16. The method of  claim 15 , wherein depositing the conductive material includes depositing conductive material over the second etched portion and extending to a second surface of the first plate outside the first and second etched portions, wherein the conductive material forms a second conductance path from the contact region to the second surface of the first plate. 
     
     
       17. The method of  claim 10 , wherein the first surface of the first plate defines a first pad of the chip. 
     
     
       18. The method of  claim 16 , wherein the first and second surfaces of the first plate outside the first and second etched portions define first and second pads of the chip.