Method and apparatus for detecting a tamper condition and isolating a circuit therefrom

Abstract

A system is disclosed for isolating a bond pad from the rest of the circuitry of a semiconductor chip in a manner that protects the chip from applied signals that are outside the normal operating range and which tamper with the operation of the system. The system includes the use of a controllable switch for routing the signal from the bond pad to the circuit and a detector for detecting a tamper condition on the bond pad. The detection of a tamper condition causes the detector to inform the microcontroller on the chip to, for example, terminate the operation in progress, perform a controlled system shutdown, disable pre-arranged functions, or record the fact that a tamper condition occurred.

What is claimed is:  
     
       1. A method for protecting a circuit of a semiconductor chip from the application of a primary signal, the primary signal being defined by parameters, the circuit being isolated from the primary signal by isolating a bond pad from the circuit with a switch, comprising: 
       supplying the primary signal to a detector and to the switch;  
       disabling the switch to interrupt the primary signal from being applied to the circuit; and generating a tamper signal at the detector if at least one of the primary signal parameters is  
       greater than or less than a value set by the detector.  
     
     
       2. The method of  claim 1 , wherein the circuit includes a Flash EPROM. 
     
     
       3. The method of  claim 1 , wherein one of the parameters of the primary signal is the voltage of the primary signal, and the detector is a voltage detector. 
     
     
       4. The method of  claim 3 , wherein the tamper signal is generated if the voltage of the primary signal is less than a value set by the voltage detector. 
     
     
       5. The method of  claim 1 , wherein one of the parameters of the primary signal is the current of the signal, and the detector is a current detector. 
     
     
       6. The method of  claim 1 , wherein the primary signal is applied to a bond pad of an integrated circuit device. 
     
     
       7. The method of  claim 6 , wherein the bond pad is the Vpp test pad of an integrated circuit containing a Flash EPROM memory array. 
     
     
       8. The method of  claim 1 , further comprising sending the tamper signal to a logic circuit. 
     
     
       9. The method of  claim 8 , wherein the circuit performs operations and wherein the logic circuit terminates the circuit operation in progress. 
     
     
       10. The method of  claim 8 , wherein the logic circuit performs a system shutdown. 
     
     
       11. The method of  claim 8 , wherein the logic circuit records the fact that a tamper condition occurred. 
     
     
       12. The method of  claim 1 , wherein the switch includes a transistor. 
     
     
       13. The method of  claim 1 , wherein the switch is activated by a charge pumping circuit. 
     
     
       14. An apparatus for protecting a circuit on a semiconductor chip from the application of a primary signal, the primary signal being defined by parameters, comprising: 
       a detector, wherein the primary signal is input to the detector, and wherein the detector generates  
       a tamper signal if at least one of the primary signal parameters is greater than or less than  
       a value set by the detector;  
       a switch interposed between the primary signal and the circuit; and  
       a logic circuit responsive to the tamper signal.  
     
     
       15. The apparatus of  claim 14 , wherein the circuit includes a Flash EPROM. 
     
     
       16. The apparatus of  claim 14 , wherein one of the parameters of the primary signal is the voltage of the primary signal, and the detector is a voltage detector. 
     
     
       17. The apparatus of  claim 16 , wherein the tamper signal is generated if the voltage of the primary signal is less than a value set by the voltage detector. 
     
     
       18. The apparatus of  claim 14 , wherein one of the parameters of the primary signal is the current of the signal, and the detector is a current detector. 
     
     
       19. The apparatus of  claim 14 , wherein the primary signal is applied to a bond pad of an integrated circuit device. 
     
     
       20. The apparatus of  claim 19 , wherein the bond pad is the Vpp test pad of an integrated circuit containing a Flash EPROM memory array. 
     
     
       21. The apparatus of  claim 14 , wherein the circuit performs operations and wherein the logic circuit terminates the circuit operation in progress in response to the tamper signal. 
     
     
       22. The apparatus of  claim 14 , wherein the logic circuit performs a system shutdown in response to the tamper signal. 
     
     
       23. The apparatus of  claim 14 , wherein the logic circuit records the fact that a tamper condition occurred in response to the tamper signal. 
     
     
       24. The apparatus of  claim 14 , wherein the switch includes a transistor. 
     
     
       25. The apparatus of  claim 14 , wherein the switch is activated by a charge pumping circuit. 
     
     
       26. An apparatus for protecting a circuit from the application of a primary signal, the primary signal being defined by parameters, comprising; 
       means for generating a tamper signal in response to the primary signal;  
       a switch interposed between the primary signal and the circuit; and  
       a logic circuit responsive to the tamper signal.  
     
     
       27. The apparatus of  claim 26 , wherein the circuit includes a Flash EPROM. 
     
     
       28. The apparatus of  claim 26 , wherein the primary signal is applied to a bond pad of an integrated circuit device. 
     
     
       29. The apparatus of  claim 28 , wherein the bond pad is the Vpp test pad of an integrated circuit containing a Flash EPROM memory array. 
     
     
       30. The apparatus of  claim 26 , wherein the circuit performs operations and wherein the logic circuit terminates the circuit operation in progress in response to the tamper signal. 
     
     
       31. The apparatus of  claim 26 , wherein the logic circuit performs a system shutdown in response to the tamper signal. 
     
     
       32. The apparatus of  claim 26 , wherein the logic circuit records the fact that a tamper condition occurred in response to the tamper signal. 
     
     
       33. The apparatus of  claim 26 , wherein the switch includes a transistor. 
     
     
       34. The apparatus of  claim 26 , wherein the switch is activated by a charge pumping circuit.