Signal deciding apparatus

Abstract

A signal deciding apparatus which can obtain a stable digital signal OUT irrespective of an amplitude and a duty ratio of an input signal IN is provided. The input signal IN is amplified by inverters ( 5 1 to 5 3 and 8 ) and outputted as a digital signal OUT. A signal (S 5 ) on the input side of the inverter ( 8 ) is integrated by a time constant which is equal to a data period of the input signal IN by an integrator ( 9 ) and supplied to a differential amplifier ( 20 ). A signal (S 8 ) on the output side of the inverter ( 8 ) is integrated by a large time constant by an integrator ( 10 ), a control voltage VC supplied from a control terminal ( 13 ) is multiplexed to the integrated signal S 8, and a resultant signal is sent to the differential amplifier ( 20 ). An output signal of the differential amplifier ( 20 ) is integrated by a resistor ( 11 ) and a capacitor ( 4 ) and its average level is fed back as a threshold voltage to the input side of the inverter ( 5 1 ) through a resistor ( 3 ) and multiplexed to the input signal IN. Thus, the digital signal OUT based on the duty ratio of the input signal IN is obtained.

What is claimed is:  
     
       1. A signal deciding apparatus comprising: 
       an amplifying circuit which has a plurality of inverting amplifiers that are mutually serially connected and is used for converting an AC input signal into a binary digital signal; and  
       a feedback path which is used for feeding back an output signal of said amplifying circuit to an input signal thereof in order to set a threshold value for binary decision of said amplifying circuit and is equipped with a first integrating circuit for prevention of an oscillation that is caused due to the feedback signal,  
       wherein said feedback path has:  
       a second integrating circuit for integrating an output signal of one of said inverting amplifiers locating at an odd number stage when it is seen from an input side of said amplifying circuit by a predetermined time constant;  
       a third integrating circuit for integrating an output signal of one of said inverting amplifiers locating at an even number stage when it is seen from the input side of said amplifying circuit by a time constant larger than the time constant of said second integrating circuit;  
       a comparing circuit for comparing output voltages of both of said integrating circuits and supplying an output voltage to said first integrating circuit; and  
       a control circuit for applying a control voltage for setting a threshold voltage to an input terminal of said comparing circuit for receiving the output voltage of said third integrating circuit.  
     
     
       2. An apparatus according to  claim 1 , wherein said comparing circuit sets the sum of said output voltage of said third integrating circuit and said control voltage to a threshold value and, when said threshold value is larger than the output voltage of said second integrating circuit, said comparing circuit generates a low level signal to said first integrating circuit, and when said threshold value is smaller than the output voltage of said second integrating circuit, said comparing circuit generates a high level signal to said first integrating circuit. 
     
     
       3. An apparatus according to  claim 1 , wherein said amplifying circuit has an even number of inverting amplifiers, said first integrating circuit integrates an input side signal of said inverting amplifier at the final stage, and said second integrating circuit integrates an output signal of said inverting amplifier at said final stage. 
     
     
       4. An apparatus according to  claim 1 , wherein said first integrating circuit has a time constant which is almost equal to that of said third integrating circuit. 
     
     
       5. An apparatus according to  claim 1 , wherein the time constant of said second integrating circuit is almost equal to a data period of said input signal. 
     
     
       6. An apparatus according to  claim 1 , wherein the time constant of said third integrating circuit is hundreds to thousands of times as large as that of said second integrating circuit. 
     
     
       7. An apparatus according to  claim 1 , wherein said comparing circuit comprises 2n+1 (n is a natural number) operational amplifiers each of which is constructed by mutually serially connecting a depression type field effect transistor and an enhancement type field effect transistor, said 2n operational amplifiers are constructed by serially connecting them to n stages in a manner such that two operational amplifiers whose positive phase (+) sides and negative phase (−) sides are complementarily connected in parallel are used as one set, both outputs of one set of operational amplifiers constructing the set at the final stage of said n-stage connection are inputted to one (2n+1)th operational amplifier for the purpose of comparing them, and a comparison result is inputted as an output of said comparing circuit to said first integrating circuit. 
     
     
       8. An apparatus according to  claim 3 , wherein the input side signal of said inverting amplifier at the final stage of said amplifying circuit is voltage divided into a certain ratio {a/(a+b)}, its voltage division value is inputted to said second integrating circuit, the output side signal of said inverting amplifier at the final stage of said amplifying circuit is voltage divided into a ratio {b/(a+b)} obtained by subtracting said ratio from 1, and its voltage division value is inputted to said third integrating circuit.