Ultra high density series-connected transistors formed on separate elevational levels

Abstract

A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

What is claimed is:  
     
       1. A method of forming a pair of transistors having source-drain paths of said transistors connected in series to a power supply: 
       providing a first transistor of said pair having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant;  
       depositing an interlevel dielectric upon the first source implant, upon the first drain implant and upon the first gate conductor;  
       forming a second substrate within said interlevel dielectric a spaced distance above and laterally offset from said first gate conductor;  
       forming a conductive plug through said interlevel dielectric to said first drain implant, wherein said conductive plug abuts a lateral surface of said second substrate;  
       forming a second transistor of said pair having a second gate conductor arranged upon said second substrate between a second source implant and a second drain implant, wherein said second source implant is proximate to said conductive plug; and  
       patterning an interconnect across a portion of said second substrate in electrical communication with both said second substrate and said second source.  
     
     
       2. The method as recited in  claim 1 , wherein said forming the second substrate comprises: 
       etching a trench within an upper surface of the interlevel dielectric; and  
       filling the trench with a semiconductive material.  
     
     
       3. The method as recited in  claim 2 , wherein said semiconductive material is rendered conductive by implanting the semiconductive material with a dopant. 
     
     
       4. The method as recited in  claim 2 , wherein said semiconductive material comprises polycrystalline silicon. 
     
     
       5. The method as recited in  claim 1 , wherein said forming the conductive plug comprises: 
       etching an opening through a localized region of said interlevel dielectric to said first drain;  
       filling the opening within a conductive material; and  
       removing the conductive material from said interlevel dielectric while retaining said conductive material exclusively within said opening to form said conductive plug.  
     
     
       6. The method as recited in  claim 5 , wherein said conductive material comprises a material selected from the group consisting of titanium, tungsten, titanium nitride, aluminum and copper. 
     
     
       7. The method as recited in  claim 5 , wherein said conductive material comprises tungsten layered upon titanium nitride. 
     
     
       8. The method as recited in  claim 1 , wherein said second source implant extends laterally between a first sidewall surface of the second substrate and a channel beneath said second gate conductor, and wherein said second drain implant extends laterally between a second sidewall surface opposite the first sidewall surface and said channel. 
     
     
       9. The method as recited in  claim 8 , wherein a portion of said first sidewall surface abuts a lateral surface of said conductive plug. 
     
     
       10. The method as recited in  claim 1 , wherein said interconnect extends from said conductive plug to at least one contact extending to said second substrate outside of said second source and second drain implants. 
     
     
       11. A method of forming three transistors having source-drain paths of said transistors connected in series to a power supply: 
       providing a first transistor having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant;  
       depositing an interlevel dielectric upon the first source implant, upon the first drain implant and upon the first gate conductor;  
       forming a second substrate within said interlevel dielectric a spaced distance above and laterally offset from said first gate conductor;  
       forming a conductive plug through said interlevel dielectric to said first drain implant, wherein said conductive plug abuts a lateral surface of said second substrate;  
       forming a second transistor having a second gate conductor arranged upon said second substrate between a second source implant and a second drain implant, wherein said second source implant is proximate to said conductive plug;  
       depositing another interlevel dielectric upon the second source implant, upon the second drain implant and upon the second gate conductor;  
       forming a third substrate within said another interlevel dielectric a spaced distance above and laterally offset from said second gate conductor;  
       forming another conductive plug through said another interlevel dielectric to said second source implant, wherein said another conductive plug abuts a lateral surface of said third substrate;  
       forming a third transistor having a third gate conductor arranged upon said third substrate between a third source implant and a third drain implant, wherein said third drain implant is proximate to said another conductive plug; and  
       patterning an interconnect across a portion of said substrate in electrical communication with both said third substrate and said third source.