System to avoid unstable data transfer between digital systems

Abstract

A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention includes a system that enables detection of potentially unstable operating conditions for a digital receiver device during its reception of clock and digital data signals from a digital transmitter device. One embodiment of the present invention monitors the received clock and digital data signals in order to detect any potential violations of the internal input timing requirement of the digital receiver device. If any potential violations of the input timing requirement are detected, the present invention invokes measures to eliminate them by manipulating the phase of the clock signal utilized internally by the digital receiver device to sample the received digital data signals. In this manner, the present invention ensures that the digital receiver device internally operates within its input timing requirement and thereby avoids unstable operating conditions which can result in signal distortion or a loss of data. Therefore, the present invention enables digital systems to communicate while avoiding unstable data transfer.

What is claimed is:  
     
       1. A system for avoiding unstable data transfer between digital devices, said system comprising: 
       a digital transmitter device which transmits a data signal and a first clock signal; and  
       a digital receiver device coupled to receive said data signal and said first clock signal, said digital receiver device comprising:  
       a clock generator circuit coupled to receive said first clock signal and for generating a second clock signal;  
       a clock monitor circuit coupled to receive said first clock signal and said second clock signal, wherein said clock monitor circuit detects a potential unstable operating condition for said digital receiver device by monitoring the set-up time criterion and the hold time criterion of the transitions within said second clock signal;  
       in response to detecting said potential unstable operating condition, said clock monitor circuit generates an adjust signal causing said clock generator circuit to manipulate the phase of said second clock signal with respect to the phase of said first clock signal in order to remove said potential unstable operating condition; and  
       internal circuitry coupled to receive said data signal and said second clock signal.  
     
     
       2. The system as described in  claim 1  wherein said clock generator circuit manipulates the phase of said second clock signal by shifting it backward or forward with respect to the phase of said first clock signal. 
     
     
       3. The system as described in  claim 1  wherein said potential unstable operating condition is a potential input timing violation for said digital receiver device. 
     
     
       4. The system as described in  claim 1  wherein said internal circuitry comprises a register coupled to receive said data signal and said second clock signal. 
     
     
       5. The system as described in  claim 1  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing an artificial data signal having similar timing as said first clock signal. 
     
     
       6. The system as described in  claim 1  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing a plurality of registers. 
     
     
       7. The system as described in  claim 1  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing a control unit. 
     
     
       8. The system as described in  claim 7  wherein said control unit is implemented using hardware or software. 
     
     
       9. The system as described in  claim 1  wherein said digital transmitter device and said digital receiver device are located on a common circuit board. 
     
     
       10. The system as described in  claim 1  wherein said digital transmitter device and said digital receiver device are each separate digital devices. 
     
     
       11. A system for avoiding unstable data transfer between digital devices, said system comprising: 
       a digital transmitter device which transmits a data signal and a first clock signal; and  
       a digital receiver device coupled to receive said data signal and said first clock signal, said digital receiver device comprising:  
       a clock generator circuit coupled to receive said first clock signal and for generating a second clock signal based on said first clock signal;  
       a clock monitor circuit coupled to receive said first clock signal and said second clock signal, wherein said clock monitor circuit detects a potential input timing violation for said digital receiver device by monitoring the set-up time criterion and the hold time criterion of the transitions within said second clock signal;  
       in response to detecting said potential input timing violation, said clock monitor circuit generates an adjust signal causing said clock generator circuit to shift the phase of said second clock signal with respect to the phase of said first clock signal by temporarily increasing or decreasing the frequency of said second clock signal in order to remove said potential input timing violation; and  
       internal circuitry coupled to receive said data signal and said second clock signal.  
     
     
       12. The system as described in  claim 11  wherein said digital transmitter device and said digital receiver device are located on a common circuit board. 
     
     
       13. The system as described in  claim 11  wherein said digital transmitter device and said digital receiver device are each separate digital devices. 
     
     
       14. The system as described in  claim 11  herein said internal circuitry comprises a flip-flop circuit coupled to receive said data signal and said second clock signal. 
     
     
       15. The system as described in  claim 11  herein said clock monitor circuit detects said potential input timing violation for said digital receiver device utilizing an artificial data signal having similar timing as said first clock signal. 
     
     
       16. The system as described in  claim 11  wherein said clock monitor circuit detects said potential input timing violation for said digital receiver device utilizing a plurality of registers. 
     
     
       17. The system as described in  claim 11  wherein said clock monitor circuit detects said potential input timing violation for said digital receiver device utilizing a control unit. 
     
     
       18. The system as described in  claim 17  herein said control unit is implemented using hardware or software. 
     
     
       19. A method for avoiding unstable data transfer between digital devices, said method comprising: 
       transmitting a data signal and a first clock signal using a digital transmitter device;  
       receiving said data signal and said first clock signal using a digital receiver device;  
       generating a second clock signal based on said first clock signal using a clock generator circuit which is part of said digital receiver device;  
       receiving said first clock signal and said second clock signal using a clock monitor circuit which is part of said digital receiver device;  
       detecting a potential unstable operating condition for said digital receiver device by monitoring the set-up time criterion and the hold time criterion of the transitions within said second clock signal using said clock monitor circuit;  
       generating an adjust signal in response to said potential unstable operating condition, wherein said adjust signal causes said clock generator circuit to manipulate the phase of said second clock signal with respect to the phase of said first clock signal in order to remove said potential unstable operating condition, said adjust signal generated by said clock monitor circuit; and  
       receiving said data signal and said second clock signal using internal circuitry of said digital receiver device.  
     
     
       20. The method as described in  claim 19  wherein said clock generator circuit manipulates the phase of said second clock signal by shifting it backward or forward with respect to the phase of said first clock signal. 
     
     
       21. The method as described in  claim 20  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing an artificial data signal having similar timing as said first clock signal. 
     
     
       22. The method as described in  claim 19  wherein said internal circuitry comprises a register circuit. 
     
     
       23. The method as described in  claim 19  wherein said potential unstable operating condition is a potential input timing violation for said digital receiver device. 
     
     
       24. The method as described in  claim 19  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing a plurality of registers. 
     
     
       25. The method as described in  claim 19  wherein said clock monitor circuit detects said potential unstable operating condition for said digital receiver device utilizing a control unit. 
     
     
       26. The method as described in  claim 25  wherein said control unit is implemented using hardware or software.