Method and apparatus for board model correction

Abstract

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

What is claimed is:  
     
       1. A method of correcting voltage measurements for parasitic effects, comprising: 
       taking a first voltage measurement on a first node of a circuit;  
       correcting said first voltage measurement for a source parasitic effect to produce a first corrected voltage measurement;  
       correcting said first corrected voltage measurement by a correction factor; and  
       calculating said correction factor, said correction factor relating an ideal voltage to model corrected measured voltage, said ideal voltage being a voltage obtained from a model of said circuit without parasitic effects of tester hardware.  
     
     
       2. The method of claim  1 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       3. The method of claim  2 , wherein said impedance in series with said source includes a ground impedance and an input impedance, wherein said ground impedance and said input impedance are calculated using a first default value for said ground impedance and a second default value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       4. The method of claim  3 , further comprising: 
       calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       5. The method of claim  4  wherein said step of calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said step of calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       6. The method of claim  5  further comprising: 
       modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       7. The method of claim  1 , wherein said step of correcting said first voltage measurement further comprises correcting for a detector parasitic effect. 
     
     
       8. The method of claim  7 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       9. The method of claim  8 , wherein said impedance in series with said source includes a ground impedance and an input impedance and said ground impedance and said input impedance are calculated using a first default value for said ground impedance and a second default value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       10. The method of claim  9 , further comprising: 
       calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       11. The method of claim  10  wherein said step of calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said step of calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       12. The method of claim  11  further comprising: 
       modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       13. A program storage medium readable by a computer, tangibly embodying a program of instruction executable by the computer to perform method steps for correcting voltage measurements for parasitic effects, said method comprising: 
       taking a first voltage measurement on a first node of a circuit;  
       correcting said first voltage measurement for a source parasitic effect to produce a first corrected voltage measurement;  
       correcting said first corrected voltage measurement by a correction factor; and,  
       calculating said correction factor, said correction factor relating an ideal voltage to model corrected measured voltage, said ideal voltage being a voltage obtained from a model of said circuit without parasitic effects of tester hardware.  
     
     
       14. The program storage medium of claim  13 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       15. The program storage medium of claim  14 , wherein said impedance in series with said source includes a ground impedance and an input impedance and said ground impedance and said input impedance are calculated using a first default value for said ground impedance and a second default value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       16. The program storage medium of claim  15 , further comprising: 
       calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       17. The program storage medium of claim  16  wherein said step of calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said step of calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       18. The program storage medium of claim  17  further comprising: 
       modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       19. The method of claim  13 , wherein said step of correcting said first voltage measurement further comprises correcting for a detector parasitic effect. 
     
     
       20. The program storage medium of claim  19 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       21. The program storage medium of claim  20 , wherein said impedance in series with said source includes a ground impedance and in input impedance and said ground impedance and said input impedance are calculated using a first default value for said ground impedance and a second default value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       22. The program storage medium of claim  21 , further comprising: 
       calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       23. The program storage medium of claim  22  wherein said step of calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said step of calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       24. The program storage medium of claim  23  further comprising: 
       modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       25. A apparatus for correcting voltage measurements for parasitic effects, comprising: 
       means for taking a first voltage measurement on a first node of a circuit;  
       means for correcting said first voltage measurement for a source parasitic effect to produce a first corrected voltage measurement;  
       means for correcting said first corrected voltage measurement by a correction factor; and,  
       means for calculating said correction factor, said correction factor relating an ideal voltage to model corrected measured voltage, said ideal voltage being a voltage obtained from a model of said circuit without parasitic effects of tester hardware.  
     
     
       26. The apparatus of claim  25 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       27. The apparatus of claim  26 , wherein said impedance in series with said source includes a ground impedance and an input impedance and said ground impedance and said input impedance are calculated using an ideal value for said ground impedance and an ideal value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       28. The apparatus of claim  27 , further comprising: 
       means for calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       means for calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       29. The apparatus of claim  28  wherein said means for calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said means for calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       30. The apparatus of claim  29  further comprising: 
       means for modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       31. The apparatus of claim  25 , wherein said means for correcting said first voltage measurement further comprises correcting for a detector parasitic effect. 
     
     
       32. The apparatus of claim  31 , wherein said parasitic effects of tester hardware include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       33. The apparatus of claim  32 , wherein said impedance in series with said source includes a ground impedance and an input impedance and said ground impedance and said input impedance are calculated using an ideal value for said ground impedance and an ideal value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       34. The apparatus of claim  33 , further comprising: 
       means for calculating a second calculated ground impedance using said first calculated ground impedance; and,  
       means for calculating a second calculated input impedance using said second calculated input impedance.  
     
     
       35. The apparatus of claim  34  wherein said means for calculating a second calculated ground impedance using said first calculated ground impedance also includes using said first calculated input impedance, and wherein said means for calculating a second calculated input impedance using said first calculated input impedance also includes using said first calculated ground impedance. 
     
     
       36. The apparatus of claim  35  further comprising: 
       means for modeling said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.  
     
     
       37. An apparatus for testing, comprising: 
       a measuring system, said measuring system taking a first voltage measurement on a first node of a circuit;  
       a processing system, said processing system comprising at least one processor, wherein said processing system corrects said first voltage measurement for a source parasitic effect to produce a first corrected voltage measurement, and wherein said processing system corrects said first corrected voltage measurement by a correction factor, and wherein said processing system calculates said correction factor, said correction factor relating an ideal voltage to model corrected measured voltage, said ideal voltage being a voltage obtained from a model of said circuit without parasitic effects of said measuring system.  
     
     
       38. The apparatus of claim  37 , wherein said parasitic effects of said measuring system include impedance in series with a source, inaccuracies in a reference resistor, and inaccuracies in said source. 
     
     
       39. The apparatus of claim  38 , wherein said impedance in series with said source includes a ground impedance and an input impedance and said ground impedance and said input impedance are calculated using an ideal value for said ground impedance and an ideal value for said input impedance to produce a first calculated ground impedance and a first calculated input impedance. 
     
     
       40. The apparatus of claim  39  wherein said processing system calculates a second calculated ground impedance using said first calculated ground impedance, and wherein said processing system calculates a second calculated input impedance using said second calculated input impedance. 
     
     
       41. The apparatus of claim  40  wherein said processing system calculates said second calculated ground impedance using said first calculated input impedance, and said processing system calculates said second calculated input impedance using said first calculated ground impedance. 
     
     
       42. The apparatus of claim  41  wherein said processing system models said circuit with said second calculated ground impedance and said second calculated input impedance and a measured value of said source and a calculated value of said reference resistor to produce said model corrected measured voltage.