Polycrystalline silicon carbide ceramic wafer and substrate

Abstract

A substrate made of polycrystalline βSiC and having an essentially pore free surface is disclosed. The substrate is adapted for use as a wafer component to support different thinfilms as part of manufacturing for discrete or integrated circuit electronic devices. The substrate comprises a polycrystalline silicon carbide outer surface with {111} crystal planes exposed on the working surface, the outer surface is essentially pore free or without exposed pores, scratches, steps or other such depressions or discontinuities on the surface of the substrate having at least one dimension larger than 2.54 microns, and no non-stoichiometric silicon or carbon other than that which may be residual from the process of making silicon carbide ceramic material.

What is claimed is:  
     
       1. A wafer structure component used in the making of discrete or integrated circuit devices comprising a working surface, at least a portion of the working surface comprising a polycrystalline beta silicon carbide outer surface with {111} crystallographic planes exposed on the working surface, the portion of the working surface being without exposed pores, scratches, steps, or other such depressions or discontinuities on the surface of the substrate having at least one dimension larger than 0.1 micron, and no non-stoichiometric silicon or carbon other than that which may be residual from the process of making silicon carbide ceramic material. 
     
     
       2. The substrate of claim  1  wherein the substrate is finished to <5 Å Ra on the portion that is the working surface side or “face” and <20 Å Ra on a surface opposite the working surface or “back” side. 
     
     
       3. The substrate of claim  1  wherein the substrate is finished to <0.4 microns Ra on both sides for use as a test wafer. 
     
     
       4. A beta silicon carbide substrate comprising a top and bottom surface, the top surface having an exposed polycrystalline {111} crystallographic plane, and being without exposed pores, scratches, steps, or other such depressions or discontinuities on the surface of the substrate having at least one dimension larger than 2.54 microns, and no non-stoichiometric silicon or carbon other than that which may be residual from the process of making silicon carbide ceramic material. 
     
     
       5. The substrate of claim  4 , wherein the dimension is no larger than 0.1 micron. 
     
     
       6. A laminate comprising the substrate of claim  1  and a non-magnetic thin film coating on the outer surface. 
     
     
       7. The laminate of claim  6  wherein the thin film coating is selected from the group consisting of a metallic material, an electrical insulating material, a ferroelectric material, a resistive material, a semiconductor material, a light emitting material, and a light sensing material. 
     
     
       8. An integrated circuit electronic device including the laminate structure of claim  7 . 
     
     
       9. A discrete device including the laminate structure of claim  7 . 
     
     
       10. The laminate of claim  7 , wherein the substrate is finished to <5 Å Ra on a portion of the wafer that is used to support the laminates and <20 Å Ra on the surface opposite the working surface. 
     
     
       11. The laminate of claim  7 , wherein the metallic material contains gold, aluminum, silver, or copper. 
     
     
       12. The laminate of claim  7 , wherein the electrical insulating material is one of silicon monoxide, silicon dioxide, silicon nitride, or beryllium oxide. 
     
     
       13. The laminate of claim  7 , wherein the ferroelectric material is one of tantalum dioxide, barium ferrite, or perovskite. 
     
     
       14. The laminate of claim  7 , wherein the semiconductor layer is at least one of beta silicon carbide, gallium nitride, indium nitride or aluminum nitride. 
     
     
       15. The laminate of claim  7 , wherein the light emitting material or the light sensing material is selected from the group consisting of gallium nitride, indium nitride, aluminum nitride, and a composition containing two or more of gallium nitride, indium nitride, or aluminum nitride. 
     
     
       16. The laminate of claim  14 , wherein the semiconductor layer is beta silicon carbide containing nitrogen or phosphorous in as n-type dopants for carrier concentration modification. 
     
     
       17. The laminate of claim  14 , wherein the semiconductor layer is beta silicon carbide containing aluminum or boron as p-type dopants for hole concentration modification. 
     
     
       18. The laminate of claim  14 , wherein the semiconductor layer is a material selected from the group consisting of gallium nitride, indium nitride, aluminum nitride, and a composition containing two or more of gallium nitride, indium nitride, or aluminum nitride, the material containing silicon as an n-type dopant for carrier concentration modification. 
     
     
       19. The laminate of claim  14 , wherein the semiconductor layer is a material selected from the group consisting of gallium nitride, indium nitride, aluminum nitride, and a composition containing two or more of gallium nitride, indium nitride, or aluminum nitride, the material containing magnesium as an p-type dopant for hole concentration modification. 
     
     
       20. The laminate of claim  7 , wherein the semiconductor layer is a composition containing two or more of gallium nitride, indium nitride, or aluminum nitride.