MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and production process

Abstract

A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and a process for producing the transistor. The MOS transistor can be used as a selection transistor in a single-transistor memory cell having nitride spacers, or another spacer material acting as an oxidation barrier. The transistor also has a bird's beak in the gate oxide to reduce leakage currents. The production process enables the bird's beak to be produced before the nitride spacers are produced. The MOS transistor can be used in a DRAM, particularly as a selection transistor.

We claim:  
     
       1. A process for producing an MOS transistor in a semiconductor substrate which comprises: 
       producing a gate oxide on a surface of a semiconductor substrate;  
       producing a gate on the gate oxide, and producing the gate with a side wall;  
       performing a passivation step to passivate the side wall of the gate;  
       subsequently, forming a thickened area of the gate oxide below the side wall of the gate by performing an oxidation step;  
       subsequently, creating an oxidation barrier by forming a nitride spacer on the side wall of the gate; and  
       producing doped regions adjacent the gate and adjacent the surface of the semiconductor and which form a source region and a drain region of an MOS-transistor.  
     
     
       2. The process according to claim  1 , wherein the oxidation step is performed at a temperature from 700° C. to 900° C. 
     
     
       3. The process according to claim  1 , wherein the oxidation step is a wet oxidation step. 
     
     
       4. The process according to claim  1 , wherein the oxidation step is performed at a temperature from 700° C. to 900° C., and is performed as a wet oxidation. 
     
     
       5. The process according to claim  1 , which comprises, after performing the oxidation step, performing LDD implantation. 
     
     
       6. The process according to claim  1 , which comprises performing the passivation step at a temperature of at least 1000° C. 
     
     
       7. The process according to claim  1 , which comprises performing the passivation step at a temperature from 1000° C. to 1150° C. 
     
     
       8. The process according to claim  1 , which comprises, producing the gate with a tungsten silicide layer.