Cache memory accessible for continuous data without tag array indexing

Abstract

A tag array includes, corresponding to each line, backward and forward links for holding line numbers for storing adjacent data included in continuous data. For storing the continuous data in the tag array and a data array, backward and forward links are generated by holding beforehand storing line numbers used immediately before. For reading the continuous data from the tag array and the data array, by holding beforehand the content of a forward link in a line accessed immediately before, a number of a line for storing next data in the continuous data is specified without indexing a cache memory.

What is claimed is:  
     
       1. A cache memory which holds, for each continuous data, at least one of a forward relationship and a backward relationship between adjacent data included in said each continuous data, wherein said cache memory includes a tag array, 
       wherein a line number of each conti uous data is definable such that each continuous data is accessed without indexing said tag array of the cache memory during accessing to the continuous data, and  
       wherein the cache memory receives a continuous data signal.  
     
     
       2. The cache memory of claim  1 , wherein said cache memory comprises a two-way set associative type cache memory. 
     
     
       3. The cache memory of claim  2 , wherein said tag array holds first and second groups of tags for each set. 
     
     
       4. The cache memory of claim  3 , wherein said tags in said tag array include a valid bit, a backward link representing any said backward relationship, and a forward link indicating any said forward relationship. 
     
     
       5. A cache memory, comprising: 
       a tag array which includes at least two lines; and  
       a data array corresponding to said tag array,  
       wherein, for each continuous data, said tag array includes, for each of said lines, a backward link indicating a number of a line for storing backward data included in corresponding continuous data, and a forward link indicating a number of a line for storing forward data included in said corresponding continuous data,  
       wherein a line number of each continuous data is definable such that each continuous data is accessed without indexing said tag array of the cache memory during accessing to the continuous data,  
       wherein the cache memory receives a continuous data signal.  
     
     
       6. A cache memory according to claim  5 , further comprising: 
       a control circuit for setting, when data with respect to a cache miss-hit read from a main storage is stored, if data to be accessed is a first data in said continuous data, a backward link of its storing line to a null data, and setting, if said data to be accessed is data other than said first data included in said continuous data, a backward link of its storing line to indicate a previously accessed backward line and a forward link of said backward line to indicate said storing line.  
     
     
       7. A cache memory according to claim  5 , further comprising: 
       a link register for holding, when said continuous data in said cache memory is stored, a previously accessed line number which indicates a content of a backward link in a line used for next accessing to said continuous data.  
     
     
       8. A cache memory according to claim  7 , further comprising: 
       a control circuit for setting, when data from a main storage with respect to a cache miss-hit is stored, if data to be accessed is first data in said continuous data, a backward link of its storing line to a null data, and setting, if said data to be accessed is data other than said data included in said continuous data, a content of said link register in a backward link of its storing line and a forward link of its backward line to indicate said storing line.  
     
     
       9. A cache memory according to claim  5 , further comprising: 
       a link register for holding, when said continuous data from said cache memory is read, a content of a previously accessed line's forward link which indicates a line number for next accessing to said continuous data.  
     
     
       10. A cache memory according to claim  9 , further comprising: 
       a control circuit for performing control so as to index, when data from said cache memory with respect to a cache hit is read, if data to be accessed is a first data in said continuous data, said cache memory and access, if said data to be accessed is data other than said data included in said continuous data, a line indicated by said link register.  
     
     
       11. A cache memory according to claim  5 , further comprising: 
       a link register for holding, when said continuous data in said cache memory is stored, a number of a previously accessed line and indicating a content of a backward link in a line used for next accessing to said continuous data, and holding, when said continuous data from said cache memory is read, a content of a previously accessed line's forward link which indicates a number of a line used for next accessing to said continuous data.  
     
     
       12. The cache memory of claim  5 , wherein said cache memory comprises a two-way set associative type cache memory. 
     
     
       13. The cache memory of claim  12 , wherein said tag array holds first and second groups of tags for each set. 
     
     
       14. The cache memory of claim  13 , wherein said tags in said tag array include a valid bit, a backward link representing any said backward relationship, and a forward link indicating any said forward relationship. 
     
     
       15. A continuous data storing method in a cache memory including a tag array, a data array corresponding to said tag array and a link register for holding a number of a previously accessed line for continuous data, said tag array including, for each continuous data, a backward link indicating a number of a line for storing backward data included in corresponding continuous data and a forward link indicating a number of a line for storing forward data included in said corresponding continuous data, said continuous data storing method comprising: 
       invalidating, if data to be accessed comprises a first data included in the continuous data, a backward link in its storing line; and  
       storing, if data to be accessed comprises data other than said first data included in said continuous data, a content of said link register in a backward link of its storing line and a number of its storing line in a forward link of a line indicated by said link register,  
       wherein a line number of each continuous data is definable such that each continuous data, is accessed without indexing said tag array of the cache memory during accessing to the continuous data,  
       wherein the continuous data is stored when a continuous data signal is asserted.  
     
     
       16. The method of claim  15 , wherein said cache memory comprises a two-way set associative type cache memory, and said tag array holds first and second groups of tags for each set. 
     
     
       17. The method of claim  16 , tags in said tag array include a valid bit, a backward link representing any said backward relationship, and a forward link indicating any said forward relationship. 
     
     
       18. A continuous data reading method in a cache memory, said cache memory including a tag array, a data array corresponding to said tag array, said tag array including, for each continuous data, a backward link indicating a number of a line for storing backward data included in corresponding continuous data and a forward link indicating a number of a line for storing forward data included in said corresponding continuous data, and a link register for holding a content of said forward link in a previously accessed line, said continuous data reading method comprising: 
       retrieving said cache memory if data to be accessed comprises a first data included in the continuous data; and  
       accessing a line indicated by said link register if data to be accessed comprises data other than said first data included in said continuous data,  
       wherein a line number of each contiuous data is definable such that each continuous data is accessed without indexing said tag array of the cache memory during accessing to the continuous data,  
       wherein the continuous data is read when a continuous data signal is asserted.  
     
     
       19. The method of claim  18 , wherein a cache memory comprises a two-way set associative type cache memory, and said tag array holds first and second groups of tags for each set. 
     
     
       20. The method of claim  19 , wherein said tags in said tag array include a valid bit, a backward link representing any said backward relationship, and a forward link indicating any said forward relationship.