Multi-level flash memory using triple well process and method of making

Abstract

A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:  
     
       1. A method of manufacturing a multi-level flash memory cell a semiconductor substrate, said method comprising the steps of: 
       (a) forming a deep n-well in said semiconductor substrate;  
       (b) forming a p-well within said deep n-well;  
       (c) forming a gate oxide layer on semiconductor substrate;  
       (d) forming a first polysilicon layer over said gate oxide layer;  
       (e) patterning and etching said first polysilicon layer and said gate oxide layer to form an intermediate structure within the width of said p-well;  
       (f) forming a first dielectric layer over said intermediate structure;  
       (g) depositing a second polysilicon layer over said first dielectric layer;  
       (h) etching back said second polysilicon layer to form two polysilicon sidewall spacers adjacent said intermediate structure;  
       (i) forming source and drain regions adjacent said polysilicon sidewall spacers;  
       (j) forming a second dielectric layer over said semiconductor substrate;  
       (k) forming a third polysilicon layer over said second dielectric layer; and  
       (l) patterning and etching said third polysilicon layer and said second dielectric layer to form a control gate that is insulated from and extends at least over and between said two polysilicon sidewall spacers.  
     
     
       2. The method of claim  1  wherein said first dielectric layer is ONO. 
     
     
       3. The method of claim  1  wherein said second dielectric layer is ONO. 
     
     
       4. The method of claim  2  wherein said second dielectric layer is ONO.