US6147639AExpiredUtility

Slow speed pulse chase apparatus

Assignee: US AIR FORCEPriority: Apr 16, 1986Filed: Apr 16, 1986Granted: Nov 14, 2000
Est. expiryApr 16, 2006(expired)· nominal 20-yr term from priority
G01S 13/003H01Q 3/26G01S 13/48H01Q 25/00
28
PatentIndex Score
0
Cited by
18
References
8
Claims

Abstract

A slow speed pulse chase apparatus in a bistatic radar system, wherein the receive antenna follows the transmit pulse out in space. The receive beam comprises many parallel beams that overlap all the possible positions of the transmit pulse as it travels into space. Slow speed chase apparatus provides a small group of beams which are held in a fixed location as the transmit pulse travels by and then is jumped in one large step to continue to the next position to remain there until the transmit pulse travels by.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A slow speed pulse chase apparatus for a bistatic radar system comprising in combination: a transmitter means to emit a radar signal,   a plurality of radar receivers to provide a plurality of receiving beams, said plurality of receiving beams comprising a sector array, said sector array covering a predetermined degrees of azimuthal coverage, said sector array scanning said azimuthal coverage in a predetermined number of steps, and,   a plurality of T/R modules operatively connected to said plurality of radar receivers to cooperatively form said plurality of receiving beams, said plurality of T/R modules generating steering and timing signals to sweep the zone of said azimuthal coverage in a predetermined time, each T/R of said plurality of T/R modules respectively comprise in combination: a microprocessor to receive clock signals and steering commands, said microprocessor generating beam phase signals,   a latch means operatively connected to said microprocessor to receive and store said beam phase signals,   a sequencer means to receive a beam update signal from a receiver in said plurality of radar receivers, said sequencer means generating a sequence signal,   a first and second multiplexer means operatively connected respectively to said latch means and said sequencer means, said first and second multiplexer means receiving said beam phase signals and said sequence signal, said first and second multiplexer means combining said beam phase signals and said sequence signal in a beam phase/position signal,   a first and second RAM operatively connected respectively to said first and second multiplexer means to receive therefrom said beam phase/position signal, said first and second RAM respectively storing said beam phase/position signal,   a driver means operatively connected to said first and second RAM to receive said beam phase/position signal,   a phase shifter means operatively connected to said driver means to receive said beam phase/position signal therefrom, said phase shifter means operatively connected to said bistatic radar system,   radiator means for transmitting and receiving radar signals, and,   a switching means operatively connected between said phase shifter means and said radiator means, said switching means alternatively providing a first and second signal path between said phase shifter means and said radiator means upon receipt of a T/R command signal.     
     
     
       2. A slow speed pulse chase apparatus as described in claim 1 wherein said plurality of receiving beams comprise six beams. 
     
     
       3. A slow speed pulse chase apparatus as described in claim 1 wherein said predetermined degrees of azimuthal coverage equals 95 degrees. 
     
     
       4. A slow speed pulse chase apparatus as described in claim 1 wherein said plurality of T/R modules equal 10,000 modules. 
     
     
       5. A slow speed pulse chase apparatus as described in claim 1 wherein said predetermined number of radar receivers equals 6. 
     
     
       6. A slow speed pulse chase apparatus as described in claim 1 wherein said phase shifter means comprises a pin diode switch means. 
     
     
       7. A slow speed pulse chase apparatus as described in claim 1 wherein said first path comprises a transmit path and said second path comprises a receive path. 
     
     
       8. A slow speed pulse chase apparatus as described in claim 1 wherein said each of first and second RAM units comprise a 128 word×8 bit chip.

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