Circuit arrangement for protection of HF-input-circuit on telecommunications devices

Abstract

The fine protection circuit arrangement is to reduce the remaining residual impulses on gas tube charge eliminators. This is to be achieved by means of a cascading of a gas tube charge eliminator or a λ/4 shorting stub with a fine protection circuit. The fine protection circuit connected to the gas tube circuit eliminator or λ/4 shorting stub reduces the relatively high residual voltage at the output of the gas tube charge eliminator or λ/4 shorting stub to a minimal value.

I claim: 
     
       1. A circuit for reducing residual impulses remaining on a gas tube charge eliminator and connected between said gas tube charge eliminator and a load, said circuit being a passive circuit comprising: an HF circuit for providing decoupling between said gas tube charge eliminator and said load;   two coils connected in series between an input and an output of said decoupling circuit;   a varistor connected between a common connection of said two coils and ground;   a voltage limiting diode; and   a capacitor connected in parallel to said voltage limiting diode, wherein said parallel connection of said capacitor and said voltage limiting diode is connected between said output of said circuit and said ground.   
     
     
       2. The circuit according to claim 1, wherein said decoupling circuit comprises a λ/4 shorting stub connected between said input of said decoupling circuit and said ground. 
     
     
       3. The circuit according to claim 2, wherein said HF-circuit is a quadrupol in which each of first opposite branches is formed of a serial circuit of two lines with a capacitor connected therebetween, and each of second opposite branches is formed of one line, wherein one of said first opposite branches lies in an HF-line and the other of said first opposite branches is connected in said serial circuit formed of two lines and two capacitors, the serial circuit being connected at each end to said ground. 
     
     
       4. The circuit according to claim 3, wherein said circuit is connected in parallel to said capacitor of said other one of said two branches of said quadrupol.