Comparator with a large input voltage excursion

Abstract

The present invention relates to a BICMOS technology comparator including: a first stage with differential inputs capable of operating with input voltages which are, in the common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor; a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, and a midpoint of their series connection forming an output terminal of the comparator; and circuitry for controlling the differential stages according to the voltages applied on their inputs.

What is claimed is: 
     
       1. A BICMOS technology comparator, comprising: an integrated BICMOS circuit comprising a first integrated BICMOS portion and a second integrated BICMOS portion;   the first integrated BICMOS portion having a first stage with differential inputs capable of operating with input voltages which are, in a common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor;   the second integrated BICMOS portion having a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, a midpoint of their series connection forming an output terminal of the comparator; and   means for controlling the differential stages according to the voltages applied on their inputs;   wherein said means are formed of two switches connected in series between the supply terminals, the midpoint of the series connection of the switches being connected to the output terminal and each switch including a control terminal connected to the midpoint of a series connection of a first current source with the differential stage with which the switch is associated.   
     
     
       2. The comparator of claim 1, wherein a second current source is interposed between each switch and the supply terminal associated therewith. 
     
     
       3. The comparator of claim 2, wherein each second current source is connected as a current mirror on the first current source of the differential stage with which the corresponding switch is associated. 
     
     
       4. The comparator of claim 1, wherein a control stage is interposed between each switch and the differential stage associated therewith. 
     
     
       5. The comparator of claim 4, wherein each control stage of a switch includes a third current source connected as a current mirror on the second current source associated with the other switch. 
     
     
       6. The comparator of claim 5, wherein each control stage is formed of a MOS transistor connected in series with the third current source between the supply terminals, the gate of the MOS transistor of each control stage being connected to the midpoint of the series connection of the first current source and of the differential stage with which the switch is associated. 
     
     
       7. The comparator of claim 1, wherein each switch is formed of a MOS transistor.