Stable high-dielectric-constant material electrode and method

Abstract

A structure for, and method of forming, an oxygen diffusion resistant electrode for high-dielectric-constant materials is disclosed. The electrode comprises a single grain of an oxygen stable material over a barrier layer. The single crystal oxygen stable layer is generally substantially impervious to oxygen diffusion at all relevant deposition and annealing temperatures. The disclosed structure is an integrated circuit comprising an array of microelectronic structures, with each of the microelectronic structures comprising an oxidizable layer (e.g., polysilicon 50), a barrier layer (e.g. TiN 64) overlying the oxidizable layer, a single crystal oxygen stable layer (e.g., Pt 98) overlying the barrier layer, and a high-dielectric-constant material layer (e.g., barium strontium titanate 36) overlying the oxygen stable layer. The disclosed method of fabricating an integrated circuit comprises forming an array of microelectronic structures, wherein forming each of said microelectronic structures comprises forming a barrier layer on an oxidizable layer, depositing a single crystal oxygen stable layer on the barrier layer, and depositing a high-dielectric-constant material layer on the oxygen stable layer. The single crystal oxygen stable layer prevents oxidation of the barrier layer and the oxidizable layer during subsequent processing.

What is claimed is: 
     
       1. A method of fabricating an integrated circuit, said method comprising: forming an array of microelectronic structures, wherein said forming of each of said microelectronic structures comprises forming a barrier layer on an oxidizable layerl, wherein   said oxidizable layer and said barrier layer form a plug in an opening in an interlayer dielectric formed on a semiconductor substrate, wherein   said plug is recessed below a top surface of said interlayer dielectric;   depositing a single crystal oxygen stable layer on said barrier layer, wherein said depositing of said oxygen stable layer comprises forming a train nucleus of said oxygen stable layer on a top surface of said barrier layer;   forming grain nuclei on said top surface of said interlayer dielectric;   depositing photoresist on said microelectronic structure;   planarizing said photoresist down to said top surface of said interlayer dielectric;   removing said grain nuclei from said top surface of said interlayer dielectric with a reactive ion etch; and   removing remaining portions of said photoresist from said opening; and     depositing a high-dielectric-constant material layer on said oxygen stable layer,   whereby said single crystal oxygen stable layer prevents oxidation of said barrier layer and said oxidizable layer.   
     
     
       2. The method of claim 1 wherein said opening is round. 
     
     
       3. The method of claim 1 wherein said oxygen stable layer fills and extends out of said opening. 
     
     
       4. The method of claim 1 wherein said depositing of said oxygen stable layer comprises forming a grain nucleus of said oxygen stable layer at an intersection of a top surface of said barrier layer and a side surface of said interlayer dielectric. 
     
     
       5. The method of claim 4 wherein said opening is round with a cusp, and said grain nucleus forms at said cusp. 
     
     
       6. The method of claim 1, wherein said depositing of said oxygen stable layer further comprises using selective chemical vapor deposition to complete said oxygen stable layer. 
     
     
       7. The method of claim 1 wherein said depositing of said oxygen stable layer comprises first using a first deposition rate at a first substrate high temperature, followed by a faster deposition rate at a cooler substrate low temperature. 
     
     
       8. The method of claim 1 wherein said oxygen stable layer is Pt. 
     
     
       9. A method of fabricating a high-dielectric-constant material capacitor, said method comprising: forming an opening in a surface of an interlayer dielectric formed on a semiconductor substrate; forming a doped polysilicon layer in said opening;   forming a TiN layer on said doped polysilicon layer, wherein said TiN and polysilicon layers form a recessed plug in said opening;   depositing a single crystal Pt layer on said TiN layer, said Pt layer extending out of said opening, wherein said depositing of said single crystal Pt layer comprises forming a grain nucleus of Pt on an exposed surface of said TiN layer;   forming Pt grain nuclei on said surface of said interlayer dielectric;   depositing photoresist on said interlayer dielectric, said TiN layer, and said Pt nuclei;   planarizing said photoresist down to said surface of said interlayer dielectric;   removing said grain nuclei from said surface of said interlayer dielectric with a reactive ion etch; and   removing remaining portions of said photoresist from said opening;     depositing a high-dielectric-constant material layer on said oxygen stable layer; and   depositing an upper electrode on said high-dielectric-constant material layer.   
     
     
       10. The method of claim 7 wherein said first deposition rate is between approximately 0.5 Angstroms per second and approximately 6 Angstroms per second. 
     
     
       11. The method of claim 7 wherein said first substrate temperature is approximately 600 degrees C. 
     
     
       12. The method of claim 7 wherein said faster deposition rate is approximately 30 Angstroms per second. 
     
     
       13. The method of claim 7 wherein said cooler substrate temperature is approximately 350 degrees C. 
     
     
       14. The method of claim 7 wherein said first deposition rate is between approximately 0.5 Angstroms per second and approximately 6 Angstroms per second and said faster deposition rate is approximately 30 Angstroms per second. 
     
     
       15. The method of claim 7 wherein said first substrate temperature is approximately 600 degrees C. and said cooler substrate temperature is approximately 350 degrees C.