Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system

Abstract

A system and method for high speed transferring of bus operations which are preferably strictly ordered in a processing system is provided. A system and method in accordance with the present invention comprises issuing a plurality of bus operation requests by a processor and determining if a first response has been received by the same processor indicating that one of the plurality of bus operation requests should be reissued. Then, if the first response is received, the processor provides a second response indicating that at least another of the issued bus operation requests should be reissued.

What is claimed is: 
     
       1. A method for transferring bus operations in a processing system which includes at least one processor, the method comprising the steps of: (a) issuing a plurality of bus operations by the at least one processor;   (b) determining if a first response has been received by the at least one processor indicating that a first bus operation of the plurality of bus operations should be reissued; and   (c) providing a second response from the at least one processor indicating that at least another of the issued bus operations issued after the first bus operation but before a clean response for the first bus operation should be reissued, if the first response has been received.   
     
     
       2. The method of claim 1, wherein the bus operations are ordered. 
     
     
       3. The method of claim 1, wherein the bus operations are strictly ordered. 
     
     
       4. The method of claim 1, wherein the bus operations are store operations. 
     
     
       5. The method of claim 1, wherein the bus operations are cache-inhibited store operations. 
     
     
       6. The method of claim 1, further comprising a step of reissuing the first bus operation if it is determined that the first response has been received. 
     
     
       7. The method of claim 6, further comprising a step of reissuing the at least another of the issued store requests after reissuing the first bus operation. 
     
     
       8. The method of claim 1, wherein the second response from the at least one processor indicates that all of the other issued bus operations issued after the first bus operation should be reissued. 
     
     
       9. A system for transferring bus operations in a processing system including at least one processor, the system comprising: means for issuing a plurality of bus operations by the at least one processor;   means for determining if a first response has been received by the at least one processor indicating that a first bus operation of the plurality of bus operations should be reissued, the determining means being coupled to the issuing means; and   means for providing a second response from the at least one processor indicating that at least another of the issued bus operations issued after the first bus operation but before a clean response for the first bus operation should be reissued, if the first response has been received, wherein the providing means is coupled to the determining means.   
     
     
       10. A computer readable medium containing program instructions for transferring bus operations in a processing system which includes at least one processor, the program instructions comprising the steps of: (a) issuing a plurality of bus operations by the at least one processor;   (b) determining if a first response has been received by the at least one processor indicating that a first bus operation of the plurality of bus operations should be reissued; and   (c) providing a second response from the at least one processor indicating that at least another of the issued bus operations issued after the first bus operation but before a clean response for the first bus operation should be reissued, if the first response has been received.   
     
     
       11. A computer readable medium containing program instructions for transferring bus operations using a bus in a processing system which includes at least one processor which can obtain control of the bus, the program instructions comprising the steps of: (a) issuing a first and a second bus operation requests by the at least one processor;   (b) issuing the first bus operation; and   (c) determining if a response to the first bus operation has been received by the at least one processor indicating that the first bus operation should be reissued, wherein a process for retaining control of the bus for another issuing of a bus operation is initiated prior to receiving the response,   wherein a second response from the at least one processor is provided indicating that the another issued bus operation issued after the first bus operation but before a clean response for the first bus operation be reissued, if the response has been received.     
     
     
       12. A method for transferring bus operations using a bus in a processing system which includes at least one processor which can obtain control of the bus, the method comprising the steps of: (a) issuing a plurality of bus operation requests by the at least one processor;   (b) issuing a bus operation;   (c) determining if a response to the bus operation has been received by the at least one processor indicating that the issued bus operation should be reissued; and   (d) retaining control of the bus by the at least one processor for an issuing of another bus operation initiated prior to receiving the response but before receiving a clean response for the bus operation and reissuing the bus operation and the another bus operation, if the response has been received which indicates that the bus operation would be reissued.   
     
     
       13. The method of claim 12, wherein the bus operations are ordered. 
     
     
       14. The method of claim 12, wherein the bus operations are strictly ordered. 
     
     
       15. The method of claim 12, wherein the bus operations are store operations. 
     
     
       16. The method of claim 12, wherein the bus operations are cache-inhibited store operations. 
     
     
       17. A method for transferring bus operations in a processing system which includes at least one processor, the method comprising the steps of: (a) issuing a plurality of bus operations by the at least one processor;   (b) determining if a first response has been received by the at least one processor indicating that a first bus operation of the plurality of bus operations should be reissued; and   (c) providing a second response from the at least one processor indicating that at least another of the issued bus operations issued after the first bus operation but before a clean response for the first bus operation should be reissued, if the first response has been received; wherein a self-retry operation is performed when the second response causes the at least another of the issued bus operations, issued after the first bus operation but before the clean response for the first operation, to be reissued.