Closed loop and open synchronization of the phase switchings in driving a DC motor

Abstract

The synchronizing circuit of a digital drive system of an electric motor is configured to function in a closed loop or in an open loop mode by adding a minimum number of elements to the normal scheme of a closed loop synchronizing circuit. In practice, by adding only one programmable register and a pair of two-input de-multiplexers, the system is able to automatically switch from one mode of operation to the other mode. The programmable open loop mode permits compensating for the phase angle between the current flowing through the windings and the drive voltage applied thereto, as in case of a voltage mode driving.

That which is claimed is: 
     
       1. A synchronizing circuit for phase switchings of a multiphase brushless motor according to a profile stored in a form of N number of digital samples, and being selectively switchable to an open loop or closed loop mode of operation, comprising: sensing means for sensing an instantaneous position of rotor of the motor and generating a synchronizing pulse responsive thereto;   a frequency divider for a master clock signal outputting a derived clock signal having a period divided by an N factor;   a first resettable counter receiving the derived clock signal;   a second resettable counter receiving the master clock signal;   a third resettable counter having an output for pointing to one of the stored N number of digital samples;   a first register having a reset input, the first register storing an output of said first resettable counter responsive to a synchronizing pulse from said sensing means received on the reset input;   a comparator comparing the output of said first register with contents of the second resettable counter and generating a reset pulse for said second resettable counter when the compared information is equal and for generating an incrementing pulse for the third resettable counter;   a programming register storing programmed data;   a demultiplexer for receiving an output from said programming register;   a multiplexer connected to said demultiplexer and said first resettable counter for selectively providing one of an output of said demultiplexer and an output of said first resettable counter to an input of said first register; and   a forced synchronizing pulse generating circuit enabled by a logic command for generating a forced synchronizing pulse responsive to receiving a pulse from said third resettable counter when said third resettable counter reaches a value N-1, said forced synchronizing pulse for causing a loading of data from said programming register into said first register during open loop mode operation,   causing a resetting of said first resettable counter, and   causing said multiplexer to selectively provide one of the output of said demultiplexer and the output of said first resettable counter to the input of said first register.     
     
     
       2. A synchronizing circuit according to claim 1, further comprising a second programmable register having a phase shift value for resetting said third resettable counter to a certain value corresponding to a sample from the N number of digital samples from which said third resettable counter starts counting during closed loop mode operation, and for resetting the second resettable counter to a programmed value from said first programming register. 
     
     
       3. A synchronizing circuit for phase switchings of a multiphase brushless motor according to a profile stored in a form of N number of digital samples, and being selectively switchable in an open loop or closed loop mode of operation, comprising: sensing means for sensing an instantaneous position of the rotor of the motor and generating a synchronizing pulse responsive thereto;   a first resettable counter;   a second resettable counter;   a third resettable counter having an output for pointing to one of the stored N number of digital samples;   a first register storing the output of said first resettable counter responsive to a synchronizing pulse from said sensing means;   a comparator comparing the output of said first register with contents of the second resettable counter and generating a reset pulse for said second resettable counter when the compared information is equal and for generating an incrementing pulse for the third resettable counter;   a programming register storing programmed data;   a demultiplexer for receiving an output from said programming register;   a multiplexer connected to said demultiplexer and said first resettable counter for selectively providing one of an output of said demultiplexer and an output of said first resettable counter to an input of said first register; and   a forced synchronizing pulse generating circuit enabled by a logic command for generating a forced synchronizing pulse responsive to receiving a pulse from said third resettable counter when said third resettable counter reaches a value N-1.   
     
     
       4. A synchronizing circuit according to claim 3, wherein said circuit enabled by the logic command is operatively coupled so that said forced synchronizing pulse causes a loading of data from said programming register into said first register during open loop mode operation. 
     
     
       5. A synchronizing circuit according to claim 3, wherein said circuit enabled by the logic command is operatively coupled so that said forced synchronizing pulse causes a resetting of said first resettable counter. 
     
     
       6. A synchronizing circuit according to claim 3, wherein said circuit enabled by the logic command is operatively coupled so that said forced synchronizing pulse causes said multiplexer to selectively provide one of the output of said demultiplexer and the output of said first resettable counter to the input of said first register. 
     
     
       7. A synchronizing circuit according to claim 3, further comprising a frequency divider for a master clock signal outputting a derived clock signal having a period divided by an N factor. 
     
     
       8. A synchronizing circuit according to claim 7, wherein said first resettable counter receives the derived clock signal as an input; and wherein said second resettable counter receives the master clock signal as an input. 
     
     
       9. A synchronizing circuit according to claim 3, further comprising a second programmable register having a phase shift value for resetting said third resettable counter to a certain value corresponding to a sample from the N number of digital samples from which said third resettable counter starts counting during closed loop mode operation. 
     
     
       10. A synchronizing circuit according to claim 9, wherein said phase shift value of second programmable register is further for resetting the second resettable counter to a programmed value from said first programming register. 
     
     
       11. A synchronizing circuit for phase switchings of a multiphase brushless motor according to a profile stored in a form of N number of digital samples, and being selectively switchable in an open loop or closed loop mode of operation, comprising: sensing means for sensing an instantaneous position of rotor of the motor and generating a synchronizing pulse responsive thereto;   a first resettable counter;   a second resettable counter;   a third resettable counter having an output for pointing to one of the stored N number of digital samples;   a first register having a reset input, said first register storing the output of said first resettable counter responsive to a synchronizing pulse from said sensing means received on the reset input;   a comparator for comparing the output of said first register with contents of the second resettable counter and generating a reset pulse for said second resettable counter when the compared information is equal and for generating an incrementing pulse for the third resettable counter;   a programming register storing programmed data;   a demultiplexer for receiving an output from said programming register;   a multiplexer connected to said demultiplexer and said first resettable counter for selectively providing one of an output of said demultiplexer and an output of said first resettable counter to an input of said first register;   a forced synchronizing pulse generating circuit enabled by a logic command for generating a forced synchronizing pulse responsive to receiving a pulse from said third resettable counter when said third resettable counter reaches a value N-1, said forced synchronizing pulse for causing a loading of data from said programming register into said first register during open loop mode operation,   causing a resetting of said first resettable counter, and   causing said multiplexer to selectively provide one of the output of said demultiplexer and the output of said first resettable counter to the input of said first register; and     a second programming register having a phase shift value for resetting said third resettable counter to a certain value corresponding to a sample from the N number of digital samples from which said third resettable counter starts counting during operation in closed loop mode operation, and for resetting the second resettable counter to a programmed value in said first programming register.   
     
     
       12. A synchronizing circuit according to claim 11, further comprising a frequency divider for a master clock signal outputting a derived clock signal having a period divided by an N factor. 
     
     
       13. A synchronizing circuit according to claim 11, where in said first resettable counter receives the derived clock signal as an input; and wherein said second resettable counter receives the master clock signal as an input.