Distributed DRAM refreshing

Abstract

Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.

What is claimed is: 
     
       1. A method of distributed DRAM refreshing, comprising: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then   refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers, wherein refreshing said first row of memory cells is performed during a first clock cycle and refreshing said second row of memory cells is performed during a second clock cycle, said first clock cycle and said second clock cycle defining a sequence.   
     
     
       2. The method of distributed DRAM refreshing according to claim 1, wherein said first row of memory cells has a row number and said second row of memory cells has an identical row number. 
     
     
       3. The method of distributed DRAM refreshing according to claim 1, further comprising: refreshing a third row of memory cells in said first array of DRAM memory cells with said first row of sense amplifiers, after refreshing said second row of memory cells; and then   refreshing a fourth row of memory cells in said second array of DRAM memory cells with said second row of sense amplifiers.   
     
     
       4. The method of distributed DRAM refreshing according to claim 3, wherein said third row and said fourth row have an identical row number. 
     
     
       5. The method of distributed DRAM refreshing according to claim 1, wherein said first array and said second array compose a first sub-group of arrays, and, further comprising, performing a read/write operation on a third row of memory cells in a third array of DRAM memory cells with a third row of sense amplifiers, said third array of DRAM memory cells composing a second sub-group of arrays.   
     
     
       6. A method of distributed DRAM refreshing, comprising: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers;   refreshing a second row of memory cells in a second array of DRAM memory cells with said first row of sense amplifiers; and   performing a read/write operation on a third row of memory cells in a third array of DRAM memory cells with a second row of sense amplifiers,   wherein said first array and said second array compose a first sub-group of arrays and said third array of DRAM memory cells compose a second sub-group of arrays.   
     
     
       7. The method of distributed DRAM refreshing according to claim 6, wherein said first row of memory cells has a row number and said second row of memory cells has an identical row number. 
     
     
       8. The method of distributed DRAM refreshing according to claim 6, further comprising: refreshing a third row of memory cells in said first array of DRAM memory cells with said first row of sense amplifiers, after refreshing said second row of memory cells; and then   refreshing a fourth row of memory cells in said second array of DRAM memory cells with said second row of sense amplifiers.   
     
     
       9. The method of distributed DRAM refreshing according to claim 8, wherein said third row and said fourth row have an identical row number. 
     
     
       10. A semiconductor device, comprising: a first array of DRAM memory cells;   a first row of sense amplifiers coupled to said first array of DRAM memory cells;   a second array of DRAM memory cells; and   a second row of sense amplifiers coupled to said second array of DRAM memory cells,   wherein a first row of DRAM memory cells in said first array of DRAM memory cells can be undergoing a first refresh operation at the same time that a second row of DRAM memory cells in said second array of DRAM memory cells is undergoing a second refresh operation, and wherein refreshing said first row of memory cells is performed during a first clock cycle and refreshing said second row of memory cells is performed during a second clock cycle, said first clock cycle and said second clock cycle defining a sequence.   
     
     
       11. The semiconductor device of claim 10, wherein said first array of DRAM memory cells, said first row of sense amplifiers, said second array of DRAM memory cells, and said second row of sense amplifiers compose a single semiconductor chip. 
     
     
       12. The semiconductor device of claim 10, further comprising a controller coupled to both said first row of sense amplifiers and said second row of sense amplifiers. 
     
     
       13. The semiconductor device of claim 10, further comprising a circuit adapted to perform a read/write operation to said first array of DRAM memory cells while simultaneously activating said second array of DRAM memory cells. 
     
     
       14. The semiconductor device of claim 10, wherein said first array and said second array compose a first sub-group of arrays, and, further comprising, a third array of DRAM memory cells composing a second sub-group of arrays and a third row of sense amplifiers coupled to said third array of DRAM memory cells,   wherein a row of DRAM memory cells in said third array can undergo a read/write operation at the same time that both said first array of DRAM memory cells and said second array of DRAM memory cells is undergoing a refresh cycle.   
     
     
       15. An embedded DRAM memory, comprising a first array of DRAM memory cells;   a first row of sense amplifiers coupled to said first array of DRAM memory cells;   a second array of DRAM memory cells;   a second row of sense amplifiers coupled to said second array of DRAM memory cells; and   a circuit adapted to perform a read/write operation to said first array of DRAM memory cells while simultaneously activating said second array of DRAM memory cells,   wherein said first array of DRAM memory cells, said first row of sense amplifiers, said second array of DRAM memory cells, said second row of sense amplifiers, and said circuit compose a single semiconductor chip, and wherein refreshing said first row of memory cells is performed during a first clock cycle and refreshing said second row of memory cells is performed during a second clock cycle, said first clock cycle and said second clock cycle defining a sequence.   
     
     
       16. The embedded DRAM memory of claim 15, further comprising a controller coupled to said row of sense amplifiers.