Bus arbitration interface for transferring signals converted in serial

Abstract

A bus arbitration interface comprises first and second serial/parallel converting units connecting a DMA device to an LSI with a DMA controller built therein for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals, a DMA arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and a DMA device arbitration interface that is an outside interface of the DMA device.

What is claimed is: 
     
       1. A bus arbitration interface for connecting an LSI and a given device, comprising: a serial signal transferring means, connecting a DMA device to an LSI with a DMA controller built therein, for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals;   a DMA arbitration bus interface means, that is an outside interface of the LSI, provided with signal I/O pins; and   a DMA device arbitration interface means that is an outside interface of the DMA device; and   wherein said serial signal transferring means comprising a first serial/parallel converting means, mounted within the LSI, for converting the acknowledge signal supplied from the DMA controller into a serial signal so to supply the serial signal to the DMA device through said DMA arbitration bus interface means, as well as converting the request signal of the serial signal received through said DMA arbitration bus interface means into a parallel signal for every DMA device so to pass the parallel signal to the DMA controller,   a clock dividing means, mounted within the LSI, for generating an operation clock for the DMA controller, and   a second serial/parallel converting means, provided on the side of the DMA device, for converting the request signal received from the DMA device through said DMA device arbitration interface means into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every DMA device so to pass the parallel signal to the DMA device through said DMA device arbitration interface means,   wherein said serial signal transferring means sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock, in said first and second serial/parallel converting means.     
     
     
       2. A bus arbitration interface for connecting an LSI and a given device, comprising: a serial signal transferring means, connecting a DMA device to an LSI with a DMA controller built therein, for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals;   a DMA arbitration bus interface means, that is an outside interface of the LSI, provided with signal I/O pins; and   a DMA device arbitration interface means that is an outside interface of the DMA device; and   wherein said serial signal transferring means comprising a first serial/parallel converting means, mounted within the LSI, for converting the acknowledge signal supplied from the DMA controller into a serial signal so to supply the serial signal to the DMA device through said DMA arbitration bus interface means, as well as converting the request signal of the serial signal received through said DMA arbitration bus interface means into a parallel signal for every DMA device so to pass the parallel signal to the DMA controller,   a clock dividing means, mounted within the LSI, for generating an operation clock for the DMA controller by dividing an operation clock for a DMA bus which interconnects the DMA device and the LSI into the same number as that of the DMA devices controlled by the DMA controller, and   a second serial/parallel converting means, provided on the side of the DMA device, for converting the request signal received from the DMA device through said DMA device arbitration interface means into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every DMA device so to pass the parallel signal to the DMA device through said DMA device arbitration interface means,     wherein serial signal transferring means sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock for the DMA device and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock for the DMA device, in said first and second serial/parallel converting means.   
     
     
       3. A bus arbitration interface for connecting an LSI to a given device, comprising: a serial signal transferring means, connecting a bus master device to an LSI having a bus master arbitration function, for exchanging a request signal sent from the bus master device to a bus arbiter built in the LSI and an acknowledge signal sent from the bus arbiter to the bus master device as serial signals;   a bus master arbitration bus interface means, that is an outside interface of the LSI, provided with signal I/O pins; and   a bus master device arbitration interface means that is an outside interface of the bus master device; and   wherein said serial signal transferring means comprising a first serial/parallel converting means, mounted within the LSI, for converting the acknowledge signal supplied from the bus arbiter into a serial signal so to supply the serial signal to the bus master device through said bus master arbitration bus interface means, as well as converting the request signal of the serial signal received through said bus master arbitration bus interface means into a parallel signal for every bus master device so to pass the parallel signal to the bus arbiter,   a clock dividing means, mounted within the LSI, for generating an operation clock for the bus arbiter, and   a second serial/parallel converting means, provided on the side of the bus master device, for converting the request signal received from the bus master device through said bus master device arbitration interface means into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every bus master device so to pass the parallel signal to the bus master device through said bus master device arbitration interface means,   wherein serial signal transferring means sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock, in said first and second serial/parallel converting means.     
     
     
       4. A bus arbitration interface for connecting an LSI to a given device, comprising: a serial signal transferring means, connecting a bus master device to an LSI having a bus master arbitration function, for exchanging a request signal sent from the bus master device to a bus arbiter built in the LSI and an acknowledge signal sent from the bus arbiter to the bus master device as serial signals;   a bus master arbitration bus interface means that is an outside interface of the LSI, provided with signal I/O pins; and   a bus master device arbitration interface means that is an outside interface of the bus master device; and   wherein said serial signal transferring means comprising a first serial/parallel converting means, mounted within the LSI, for converting the acknowledge signal supplied from the bus arbiter into a serial signal so to supply the serial signal to the bus master device through said bus master arbitration bus interface means, as well as converting the request signal of the serial signal received through said bus master arbitration bus interface means into a parallel signal for every bus master device so to pass the parallel signal to the bus arbiter,   a clock dividing means, mounted within the LSI, for generating an operation clock for the bus arbiter by dividing an operation clock for a bus master bus interconnecting the bus master device and the LSI into the same number as that of the bus master devices controlled by the bus arbiter, and   a second serial/parallel converting means, provided on the side of the bus master device, for converting the request signal received from the bus master device through said bus master device arbitration interface means into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every bus master device so to pass the parallel signal to the bus master device through said bus master device arbitration interface means,   wherein serial signal transferring means sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock for the bus master device and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock for the bus master device, in said first and second serial/parallel converting means.     
     
     
       5. A bus arbitration interface for connecting an LSI and a given device, comprising: a serial signal transferring unit, connecting a DMA device to an LSI with a DMA controller built therein, for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals;   a DMA arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and   a DMA device arbitration interface that is an outside interface of the DMA device; and   wherein said serial signal transferring unit comprising a first serial/parallel converting unit, mounted within the LSI, for converting the acknowledge signal supplied from the DMA controller into a serial signal so to supply the serial signal to the DMA device through said DMA arbitration bus interface, as well as converting the request signal of the serial signal received through said DMA arbitration bus interface into a parallel signal for every DMA device so to pass the parallel signal to the DMA controller,   a clock dividing unit, mounted within the LSI, for generating an operation clock for the DMA controller, and   a second serial/parallel converting unit, provided on the side of the DMA device, for converting the request signal received from the DMA device through said DMA device arbitration interface into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every DMA device so to pass the parallel signal to the DMA device through said DMA device arbitration interface,   wherein said serial signal transferring unit sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock, in said first and second serial/parallel converting units.     
     
     
       6. A bus arbitration interface for connecting an LSI and a given device, comprising: a serial signal transferring unit, connecting a DMA device to an LSI with a DMA controller built therein, for exchanging a request signal sent from the DMA device to the DMA controller and an acknowledge signal sent from the DMA controller to the DMA device as serial signals;   a DMA arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and   a DMA device arbitration interface that is an outside interface of the DMA device; and   wherein said serial signal transferring unit comprising a first serial/parallel converting unit, mounted within the LSI, for converting the acknowledge signal supplied from the DMA controller into a serial signal so to supply the serial signal to the DMA device through said DMA arbitration bus interface, as well as converting the request signal of the serial signal received through said DMA arbitration bus interface into a parallel signal for every DMA device so to pass the parallel signal to the DMA controller,   a clock dividing unit, mounted within the LSI, for generating an operation clock for the DMA controller by dividing an operation clock for a DMA bus which interconnects the DMA device and the LSI into the same number as that of the DMA devices controlled by the DMA controller, and   a second serial/parallel converting unit, provided on the side of the DMA device, for converting the request signal received from the DMA device through said DMA device arbitration interface into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every DMA device so to pass the parallel signal to the DMA device through said DMA device arbitration interface,   wherein serial signal transferring unit sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock for the DMA device and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock for the DMA device, in said first and second serial/parallel converting units.     
     
     
       7. A bus arbitration interface for connecting an LSI to a given device, comprising: a serial signal transferring unit, connecting a bus master device to an LSI having a bus master arbitration function, for exchanging a request signal sent from the bus master device to a bus arbiter built in the LSI and an acknowledge signal sent from the bus arbiter to the bus master device as serial signals;   a bus master arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and   a bus master device arbitration interface that is an outside interface of the bus master device; and   wherein said serial signal transferring unit comprising a first serial/parallel converting unit, mounted within the LSI, for converting the acknowledge signal supplied from the bus arbiter into a serial signal so to supply the serial signal to the bus master device through said bus master arbitration bus interface, as well as converting the request signal of the serial signal received through said bus master arbitration bus interface into a parallel signal for every bus master device so to pass the parallel signal to the bus arbiter,   a clock dividing unit, mounted within the LSI, for generating an operation clock for the bus arbiter, and   a second serial/parallel converting unit, provided on the side of the bus master device, for converting the request signal received from the bus master device through said bus master device arbitration interface into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every bus master device so to pass the parallel signal to the bus master device through said bus master device arbitration interface,   wherein serial signal transferring unit sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock, in said first and second serial/parallel converting units.     
     
     
       8. A bus arbitration interface for connecting an LSI to a given device, comprising: a serial signal transferring unit, connecting a bus master device to an LSI having a bus master arbitration function, for exchanging a request signal sent from the bus master device to a bus arbiter built in the LSI and an acknowledge signal sent from the bus arbiter to the bus master device as serial signals;   a bus master arbitration bus interface, that is an outside interface of the LSI, provided with signal I/O pins; and   a bus master device arbitration interface that is an outside interface of the bus master device; and   wherein said serial signal transferring unit comprising a first serial/parallel converting unit, mounted within the LSI, for converting the acknowledge signal supplied from the bus arbiter into a serial signal so to supply the serial signal to the bus master device through said bus master arbitration bus interface, as well as converting the request signal of the serial signal received through said bus master arbitration bus interface into a parallel signal for every bus master device so to pass the parallel signal to the bus arbiter,   a clock dividing unit, mounted within the LSI, for generating an operation clock for the bus arbiter by dividing an operation clock for a bus master bus interconnecting the bus master device and the LSI into the same number as that of the bus master devices controlled by the bus arbiter, and   a second serial/parallel converting unit, provided on the side of the bus master device, for converting the request signal received from the bus master device through said bus master device arbitration interface into a serial signal so to send the serial signal to the LSI, as well as converting the acknowledge signal of the serial signal received from the LSI into a parallel signal for every bus master device so to pass the parallel signal to the bus master device through said bus master device arbitration interface,   wherein serial signal transferring unit sampling in parallel-to-serial signal conversion being performed at the rising edge of the operation clock for the bus master device and sampling in serial-to-parallel signal restoration being performed at the falling edge of the operation clock for the bus master device, in said first and second serial/parallel converting units.     
     
     
       9. A method for connecting an LSI and a DMA device comprising: converting a first parallel acknowledge signal supplied from a DMA controller into a first serial acknowledge signal and supplying the first serial acknowledge signal to the DMA device through a DMA arbitration bus interface;   converting a first serial request signal received through the DMA arbitration bus interface into a first parallel request signal for every DMA device and passing the first parallel request signal to the DMA controller;   converting a second parallel request signal received from the DMA device through the DMA arbitration interface into a second serial request signal and sending the second serial request signal to the LSI; and   converting a second serial acknowledge signal received from the LSI into a second parallel acknowledge signal for every DMA device and passing the second parallel acknowledge signal to the DMA device through the DMA device arbitration interface; and   wherein sampling in parallel-to-serial signal conversion is performed at the rising edge of an operation clock and sampling in serial-to-parallel signal restoration is performed at the falling edge of an operation clock.   
     
     
       10. A method for connecting an LSI and a DMA device comprising: converting a first parallel acknowledge signal supplied from a DMA controller into a first serial acknowledge signal and supplying the first serial acknowledge signal to the DMA device through a DMA arbitration bus interface;   converting a first serial request signal received through the DMA arbitration bus interface into a first parallel request signal for every DMA device and passing the first parallel request signal to the DMA controller;   dividing an operation clock for a DMA bus which interconnects the DMA device and the LSI into the same number as that of the DMA devices controlled by the DMA controller;   converting a second parallel request signal received from the DMA device through the DMA arbitration interface into a second serial request signal and sending the second serial request signal to the LSI; and   converting a second serial acknowledge signal received from the LSI into a second parallel acknowledge signal for every DMA device and passing the second parallel acknowledge signal to the DMA device through the DMA device arbitration interface; and   wherein sampling in parallel-to-serial signal conversion is performed at the rising edge of the operation clock for the DMA device and sampling in serial-to-parallel signal restoration is performed at the falling edge of the operation clock for the DMA device.