Optimized trench edge formation integrated with high quality gate formation

Abstract

A semiconductor manufacturing process is provided in which an oxidation retarding species is introduced into regions of the substrate distal from the isolation structures. A subsequent thermal oxidation process results in the formation of a gate dielectric film in which the film thickness proximal to the isolation structures is greater than the film thickness distal from the isolation structures. Broadly speaking, an isolation structure is formed in an isolation region of a semiconductor substrate. A mask is then formed on an upper surface of the semiconductor substrate. The mask covers the isolation structure and portions of the semiconductor substrate proximal to the isolation structure. A nitrogen bearing impurity distribution is then introduced into portions of the semiconductor substrate exposed by the mask. The nitrogen bearing impurity distribution therefore substantially resides within portions of the semiconductor substrate distal from the isolation structures. A gate dielectric is then formed on an upper surface of the semiconductor substrate. An oxidation rate of the distal portions of the semiconductor substrate is less than an oxidation rate of the proximal portions. In this manner, a thickness of the gate oxide is greater over the proximal portions of the substrate than over the distal portions.

What is claimed is: 
     
       1. An integrated circuit comprising: a semiconductor substrate, wherein said semiconductor substrate includes at least one isolation region;   an isolation structure formed in said isolation region of said semiconductor substrate; and   a gate dielectric layer formed on an upper surface of said semiconductor substrate, wherein said gate dielectric layer comprises a first thickness over regions of said semiconductor substrate proximal to said isolation structure, and further wherein said gate dielectric comprises a second thickness over regions of said semiconductor substrate distal from said isolation structure and said first thickness is greater than said second thickness.   
     
     
       2. The integrated circuit of claim 1, wherein said semiconductor substrate comprises a p-type epitaxial layer formed on a p+ silicon bulk, wherein a resistivity of said p-type epitaxial layer is in the range of approximately 10 to 15 Ω-cm. 
     
     
       3. The integrated circuit of claim 1, wherein said isolation structure comprises an isolation dielectric within an isolation trenched formed in said isolation region of said semiconductor substrate. 
     
     
       4. The integrated circuit of claim 3, wherein said isolation dielectric comprises silicon-oxide. 
     
     
       5. The integrated circuit of claim 1, wherein said gate dielectric layer comprises a thermal oxide. 
     
     
       6. The integrated circuit of claim 5, wherein said first thickness of said gate dielectric is in the range of approximately 30 to 100 angstroms and further wherein a second thickness of said gate dielectric is in the range of approximately 15 to 50 angstroms. 
     
     
       7. The integrated circuit of claim 1, further comprising a conductive gate structure formed on an upper surface of said gate dielectric, wherein said conductive gate structure extends over said distal and proximal regions of said semiconductor substrate.