High density shallow trench contactless nonvolitile memory

Abstract

The present invention proposes a novel structure of nonvolatile memories with recessed floating gates. A plurality of field oxides is formed on a semiconductor substrate. Buried bit lines are formed in the semiconductor substrate and beneath the field oxides. Between the field oxides over the buried bit lines, trenched floating gates are formed in the semiconductor substrate. Tunnel dielectrics are formed between the trenched floating gates and the semiconductor substrate. The interpoly dielectric is formed over the field oxides and the trenched floating gates and the control gates are formed on the interpoly dielectric. Because of the large area of the recessed tunnel dielectric and the recessed length of the channel, high-density shallow trench contactless nonvolatile memories can be achieved.

What is claimed is: 
     
       1. Nonvolatile memories with trenched gates formed on a semiconductor substrate, said memories comprising: field oxides formed on said semiconductor substrate;   buried bit lines formed beneath said field oxides in said semiconductor substrate;   trenched floating gates formed in said semiconductor substrate, said trenched floating gates are located between said field oxides over said buried bit lines;   tunnel dielectrics formed between said trenched floating gates and said semiconductor substrate, said tunnel dielectrics being formed with both ends respectively adjacent to one of said buried bit lines, and having recessed geometry conformable with the sidewall and bottom surfaces of said trenched floating gates;   an interpoly dielectric formed on said field oxides and said trenched floating gates; and   control gates formed on said interpoly dielectric.   
     
     
       2. The memories of claim 1, wherein said semiconductor substrate is a p-type substrate. 
     
     
       3. The memories of claim 1, wherein said field oxides are formed of silicon oxide with a thickness of about 500 angstroms to about 5000 angstroms. 
     
     
       4. The memories of claim 1, wherein said buried bit lines are n-type ion doped regions. 
     
     
       5. The memories of claim 4, wherein said n-type ions are selected from the group consisting of phosphorus ions, arsenic ions and antimony ions. 
     
     
       6. The memories of claim 1, wherein said trenched floating gate is formed of in-situ n-type doped polysilicon. 
     
     
       7. The memories of claim 1, wherein said trenched floating gates have rounded corners. 
     
     
       8. The memories of claim 1, wherein said tunnel oxides are formed of silicon oxynitride with a thickness of about 30 angstroms to about 250 angstroms. 
     
     
       9. The memories of claim 1, wherein said interpoly dielectric is formed of a material selected from the group consisting of tantalum pentoxide (Ta 2  O 5 ), barium strontium titanate (BST), a double film of silicon nitride and silicon oxide, and a triple film of silicon oxide, silicon nitride and silicon oxide (ONO). 
     
     
       10. The memories of claim 1, wherein said control gate is formed of a material selected from the group consisting of n-type doped polysilicon and in-situ n-type doped polysilicon.