Logic blocks with mixed low and regular Vt MOSFET devices for VLSI design in the deep sub-micron regime

Abstract

Logic books with mixed low V t and regular V t devices provide a performance gain without the large increase in stand-by power of the logic book. Low V t devices are used to gain speed, and regular V t devices are used to cut off the off-current of the logic book. The optimization of mixed V t configurations is important. No single path between an output and ground can be made of all low V t devices, and no single path between the output and V dd can be made of all low V t devices. Generally, devices that are connected to V dd and ground should be regular V t devices, a low V t devices should be connected closest to the output. All low V t devices should be appropriately reversely biased in their off states. Because its merits in standby power, speed and noise margin, such mixed-low-and-regular-V t logic books can have a wide use in VLSI designs (e.g., high performance microprocessor design).

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows: 
     
       1. Logic books with mixed low V t  and regular V t  devices to provide a performance gain without a large increase in stand-by power wherein, in a path between V dd  and ground, there must be at least one regular V t  device serving as high resistance to reduce the leakage current and the low V t  devices become reversely biased in their standby states so as to reduce its leakage current effectively, and   wherein in a path between V dd  and an output there must be at least one said regular V t  device, wherein said low V t  devices are connected to a node closest to the output, and   wherein in a path between the output and ground there must be at least one said regular V t  device, and   wherein said regular V t  devices are connected to V dd .   
     
     
       2. The logic books with mixed low V t  and regular V t  devices as recited in claim 1 wherein the mixed low V t  and regular V t  devices are metal oxide semiconductor field effect transistors (MOSFETs). 
     
     
       3. The logic books with mixed low V t  and regular V t  devices as recited in claim 2 wherein circuits of the logic books are static circuits. 
     
     
       4. The logic books with mixed low V t  and regular V t  devices as recited in claim 3 wherein one of the circuits is a NAND gate. 
     
     
       5. The logic books with mixed low V t  and regular V t  devices as recited in claim 3 wherein one of the circuits is a NOR gate. 
     
     
       6. The logic books with mixed low V t  and regular V t  devices as recited in claim 4 wherein one of the circuits is an AND-OR-INVERT logic block. 
     
     
       7. The logic books with mixed low V t  and regular V t  devices as recited in claim 3 wherein one of the circuits is an OR-AND-INVERT logic block. 
     
     
       8. The logic books with mixed low V t  and regular V t  devices as recited in claim 3 wherein one of the circuits is an ADDER circuit. 
     
     
       9. The logic books with mixed low V t  and regular V t  devices as recited in claim 3 wherein one of the circuits is a multiplexer circuit. 
     
     
       10. The logic books with mixed low V t  and regular V t  devices as recited in claim 2 wherein circuits of the logic books are dynamic circuits.