Circuit for easily testing a logic circuit having a number of input-output pins by scan path

Abstract

A scan path circuit is for use in testing a logic package designed in accordance with scan path fashion. The logic package comprises a logic circuit and a plurality of scan paths. The logic circuit has first through N-th input/output pins, where N represents a positive integer which is greater than one. The scan paths are connected in serial to one another and are connected to the logic circuit. The scan path circuit comprises first through N-th memory sections which are connected in serial to one another and which are connected to the first through the N-th input/output pins, respectively. Each of the memory sections comprises a first memory circuit and a second memory circuit. The first memory circuit of an n-th memory section supplies test input to an n-th input/output pin in a shifting mode, where n is a variable between one and N. The first memory circuit of the n-th memory section takes test output from the logic circuit through the n-th input/output pin in a normal mode. The second memory circuit of the n-th memory section holds test input in the shifting mode to prevent the test input from varying to a varied input.

What is claimed is: 
     
       1. A scan path circuit for use in testing a logic package designed in accordance with scan path fashion, said logic package comprising a logic circuit and a plurality of scan paths, said logic circuit having a plurality of input/output pins, said scan paths being connected in serial to one another and being connected to said logic circuit, wherein said scan path circuit comprises: first means operable as a part of said scan paths for supplying test input data to said input/output pins in a shifting mode, said first means taking test output data from said logic circuit through said input/output pins in a normal mode; and   second means for holding said test input data in said shifting mode to prevent said test input data from varying to varied input data.   
     
     
       2. A scan path circuit as claimed in claim 1, wherein: said scan path circuit has a first scan-in pin and a first scan-out pin each connected to said first means;   said logic package having a second scan-in pin and a second scan-out pin which are connected to said scan paths;   said first scan-in pin being connected to said second scan-out pin; and   each of said first scan-out pin and said second scan-in pin being connected to a tester which supplies said test input data to said second scan-in pin and which monitors a test output data outputted from said first scan-out pin.   
     
     
       3. A scan path circuit as claimed in claim 1, said scan path circuit having a scan-in pin and a scan-out pin each of connected to said first means, said first means being connected to said input/output pins, wherein each of said scan-out pin and said scan-in pin being connected to a tester which supplies said test input data to said scan-in pin and which monitors a test output data outputted from said scan-out pin. 
     
     
       4. A scan path circuit for use in testing a logic package designed in accordance with scan path fashion, said logic package comprising a logic circuit and a plurality of scan paths, said logic circuit having first through N-th input/output pins, where N represents a positive integer which is greater than one, said scan paths being connected in serial to one another and being connected to said logic circuit, said scan path circuit comprising first through N-th scan path section connected in serial to one another and connected to said first through said first through said N-th input/output pins, respectively, wherein an n-th scan path section comprises, where n is a variable between one and N, both of inclusive: first flip-flop means for supplying test input data to an n-th input/output pin in a shifting mode, said first flip-flop circuit taking test output data from said logic circuit through said n-th input/output pins in a normal mode; and   second flip-flop means connected to said first flip-flop means for holding said test input data in said shifting mode to prevent said test input data from varying to varied input data.   
     
     
       5. A scan path circuit as claimed in claim 4, wherein: said first and said second flip-flop means operates in accordance with first and second clock signals, respectively, and   said first and second clock signals being different from each other.   
     
     
       6. A scan path circuit as claimed in claim 4, said first flip-flop means having a control terminal, wherein said first flip-flop means becomes said shifting mode when a control signal is supplied to said control terminal, otherwise said first flip-flop means becomes said normal mode. 
     
     
       7. A scan path circuit as claimed in claim 4, wherein said n-th scan path section further comprises path means for allowing said test input data to pass therethrough and thereby to supply said test input data to said n-th input/output pin when said n-th input/output pin is operable as an input pin, said path means preventing supply of said test input data to said n-th input/output pin when said n-th input/output pin is operable as an output pin. 
     
     
       8. A scan path circuit as claimed in claim 4, said first flip-flop means having first primary and first subsidiary input terminals and first output terminal, said second flip-flop means having a second input terminal and a second output terminal, wherein: said n-th scan path section further comprises a buffer circuit located between said second flip-flop means and said n-th input/output;   said first primary input terminal being connected to said n-th input/output terminal in said n-th scan path section;   said first subsidiary input terminal of said n-th scan path section being connected to said first output terminal of a (n+1)-th scan path section;   said first output terminal being connected to said second input terminal in said n-th scan path section;   said second output terminal being connected to said buffer circuit; and   said buffer circuit for allowing the output of said second flip-flop means as said test input data to pass therethrough when said n-th input/output pin is operable as an input pin, said buffer circuit preventing supply of said test input data to said n-th input/output pin when said n-th input/output pin in operable as an output pin.