Method for manufacturing a capacitor

Abstract

A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a first sacrificial layer over the first conducting layer, b) partially removing the first sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the first sacrificial layer and in the contact window, d) forming a second sacrificial layer over the second conducting layer, e) partially removing the second sacrificial layer, the second conducting layer, and the first sacrificial layer to expose a portion of the first sacrificial layer, f) forming a third conducting layer alongside the second sacrificial layer, the second conducting layer, and the portion of the first sacrificial layer, g) removing the first and second sacrificial layers to expose the first conducting layer, and h) partially removing the first conducting layer while retaining a portion of the first conducting layer under the second and third conducting layers to construct a capacitor plate with a generally cross-sectionally modified H-shaped structure. This structure can effectively increase the surface area of the capacitor.

What is claimed is: 
     
       1. A method for manufacturing a capacitor applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, comprising steps of: a) forming a first sacrificial layer over said first conducting layer;   b) partially removing said first sacrificial layer, said first conducting layer, and said dielectric layer to form a contact window;   c) forming a second conducting layer over said first sacrificial layer and in said contact window;   d) forming a second sacrificial layer over said second conducting layer;   e) partially removing said second sacrificial layer, said second conducting layer, and said first sacrificial layer to expose a portion of said first sacrificial layer;   f) forming a third conducting layer alongside said second sacrificial layer, said second conducting layer, and said portion of said first sacrificial layer;   g) removing said first and second sacrificial layers to expose said first conducting layer; and   h) partially removing said first conducting layer while retaining a portion of said first conducting layer under said second and third conducting layers to construct a capacitor plate.   
     
     
       2. A method according to claim 1 wherein said dielectric layer is formed by a chemical vapor deposition (CVD). 
     
     
       3. A method according to claim 1 wherein said dielectric layer is a nondoped silicon glass (NSG) layer with a thickness ranged between 1000 Å and 3000 Å. 
     
     
       4. A method according to claim 1 wherein said first conducting layer is formed by a chemical vapor deposition. 
     
     
       5. A method according to claim 1 wherein said first conducting layer is one of a doped polysilicon layer and an amorphous silicon layer. 
     
     
       6. A method according to claim 1 wherein said first conducting layer has a thickness ranged between 100 Å and 300 Å. 
     
     
       7. A method according to claim 1 wherein in said step (a), said first sacrificial layer is formed by a chemical vapor deposition. 
     
     
       8. A method according to claim 1 wherein said first sacrificial layer is a sacrificial oxide with a thickness more than 6000 Å. 
     
     
       9. A method according to claim 1 wherein in said step (b), said contact window is formed by a photolithography and an etching technique. 
     
     
       10. A method according to claim 1 wherein in said step (c), said second conducting layer is formed by a chemical vapor deposition. 
     
     
       11. A method according to claim 1 wherein said second conducting layer is one of a doped polysilicon layer and an amorphous silicon layer. 
     
     
       12. A method according to claim 1 wherein said second conducting layer has a thickness ranged between 1000 Å and 3000 Å. 
     
     
       13. A method according to claim 1 wherein in said step (d), said second sacrificial layer is a sacrificial oxide formed by a chemical vapor deposition. 
     
     
       14. A method according to claim 1 wherein in said step (e), said second sacrificial layer, said second conducting layer, and said first sacrificial layer are partially removed by a photolithography and an etching technique. 
     
     
       15. A method according to claim 1 wherein said third conducting layer is one of a doped polysilicon layer and an amorphous silicon layer. 
     
     
       16. A method according to claim 1 wherein said third conducting layer has a thickness ranged between 1000 Å and 3000 Å. 
     
     
       17. A method according to claim 1 wherein said step (f) further includes: f1) forming a third conducting layer over surfaces of said second conducting layer, said portion of said first sacrificial layer, and said second sacrificial layer; and   f2) executing an anisotropic etching process to partially remove said third conducting layer while retaining a portion of said third conducting layer alongside said second sacrificial layer, said second conducting layer, and said portion of said first sacrificial layer.   
     
     
       18. A method according to claim 17 wherein in said step (f1), said third conducting layer is formed by a chemical vapor deposition. 
     
     
       19. A method according to claim 1 wherein in said step (g), said first and second sacrificial layers are removed by a wet etching using a buffer over etching (B.O.E.) solution containing hydrofluoric acid (HF). 
     
     
       20. A method according to claim 1 further comprising steps after said step (h): i) forming an another dielectric layer over surfaces of said portion of said first conducting layer, and said second and third conducting layers; and   j) forming a fourth conducting layer over said another dielectric layer to serve as an another capacitor plate.   
     
     
       21. A method according to claim 20 wherein said another dielectric layer and said fourth conducting layer are formed by a chemical vapor deposition (CVD). 
     
     
       22. A method according to claim 20 wherein said another dielectric layer is an oxide-on-nitride-on-oxide (ONO) layer with a thickness ranged between 50 Å and 200 Å. 
     
     
       23. A method according to claim 20 wherein said fourth conducting layer is a doped polysilicon layer. 
     
     
       24. A method according to claim 1 further comprising a step after said step (h) to form a rugged conducting layer on said portion of said first conducting layer and said second and third conducting layers.