Circuit with multiple output voltages for multiple analog to digital converters

Abstract

A circuit for generating at least two output voltages in response to an input current. A first stage comprises a first impedance for providing a first output voltage when the input current passes through the first impedance. At least a second stage comprises a second impedance coupled to the first impedance, wherein the second impedance provides a second stage voltage when the input current passes through the second impedance. At least a second output voltage is equal to the sum of the second stage voltage and the first output voltage. The second stage further comprises a second stage shunt operable to shunt the input current away from the second impedance when the magnitude of the second output voltage is above a predetermined amount.

What is claimed is: 
     
       1. A method for generating at least two variable output voltages in response to a variable input current, comprising the steps of: providing a first output voltage when the variable input current passes through a first impedance;   providing a second stage voltage when the variable input current passes through a second impedance, wherein a second output voltage equal to the sum of the first output voltage and the second stage voltage is produced; and   automatically shunting the variable input current away from the second impedance while still applying the variable input current to the first impedance when the magnitude of the second output voltage is above a predetermined amount.   
     
     
       2. The method of claim 1, wherein the step of shunting the input current away from the second impedance includes activating a transistor when the input current is above a predetermined amount. 
     
     
       3. The method of claim 1, further comprising the step of providing a third stage voltage when the input current passes through a third impedance, wherein a third output voltage equal to the sum of the third stage voltage and the second output voltage is produced. 
     
     
       4. The method of claim 3, further comprising the step of shunting the input current away from the third impedance when the magnitude of the third output voltage is above a second predetermined amount. 
     
     
       5. The method of claim 4, wherein the step of shunting the input current away from the third impedance includes activating a second transistor when the input current is above a predetermined amount.