Circuit for synchronizing asynchronous inputs using dual edge logic design

Abstract

A synchronizing circuit processes a plurality (N) of input signals to generate a synchronizing circuit output signal, and provides the synchronizing circuit output signal synchronous to a system clock, wherein the N input signals are asynchronous to the system clock. Input stage circuitry samples the N asynchronous input signals. Combinatorial logic circuitry receives and combines the sampled asynchronous input signals to generate the synchronizing circuit output signal. First polarity edge flip flop circuitry to receive, as first polarity edge flip flop input, a first output of at least a first portion of the combinatorial logic circuitry, wherein the first polarity edge flip flop circuitry processes the first polarity edge flip flop input responsive to a first polarity edge of the system clock signal to provide a first polarity edge processed output signal. Second polarity edge flip flop circuitry to receive, as second polarity edge flip flop input, the second polarity edge processed output signal and to process the second polarity edge flip flop input responsive to a second polarity edge of the system clock signal to provide a second polarity edge processed output signal. The combinatorial logic circuitry includes a second portion to process at least the second polarity edge processed output signal to generate the synchronizing circuit output signal.

What is claimed is: 
     
       1. A synchronizing circuit that processes a plurality (N) of input signals to generate a synchronizing circuit output signal, and provides the synchronizing circuit output signal synchronous to a system clock, wherein the N input signals are asynchronous to the system clock, the circuit comprising: input stage circuitry that samples the N asynchronous input signals;   combinatorial logic circuitry that receives and combines the sampled asynchronous input signals to generate the synchronizing circuit output signal;   first polarity edge flip flop circuitry to receive, as first polarity edge flip flop input, a first output of at least a first portion of the combinatorial logic circuitry, wherein the first polarity edge flip flop circuitry processes the first polarity edge flip flop input responsive to a first polarity edge of the system clock signal to provide a first polarity edge processed output signal;   second polarity edge flip flop circuitry to receive, as second polarity edge flip flop input, the second polarity edge processed output signal and to process the second polarity edge flip flop input responsive to a second polarity edge of the system clock signal to provide a second polarity edge processed output signal;   wherein the combinatorial logic circuitry includes a second portion to process at least the second polarity edge processed output signal to generate the synchronizing circuit output signal.   
     
     
       2. The synchronizing circuit of claim 1, wherein the input stage circuitry includes N input stage flip flop circuits, each of the N input stage flip flop circuits having a data input connected to received a corresponding one of the N asynchronous input signals, a clock input coupled to receive the system clock signal, and an output at which the sampled asynchronous input signal is provided synchronous to a first polarity edge of the system clock.   
     
     
       3. The synchronizing circuit of claim 1, wherein: the first portion of combinatorial logic circuitry provides N first portion combinatorial outputs, each first portion combinatorial output corresponding to a separate one of the N asynchronous inputs; and   the first polarity edge triggered flip flop circuitry includes N first polarity edge triggered flip flop circuits, each including: an input for receiving a separate one of the N first portion combinatorial outputs;   a clock input for receiving the system clock signal; and   a data output at which the received first portion combinatorial output is provided to the second polarity edge flip flop circuitry, as a first polarity edge triggered flip flop output, responsive to the first polarity edge of the system clock at the clock input.     
     
     
       4. The synchronizing circuit of claim 3, wherein: the second polarity edge triggered flip flop circuitry includes N second polarity edge triggered flip flop circuits, each including: an input for receiving a separate corresponding one of the N first polarity edge triggered flip flop outputs;   a clock input for receiving the system clock signal; and   a data output at which the received one of the N first polarity edge triggered flip flop outputs is provided to the second portion of the combinatorial circuitry, as a second polarity edge triggered flip flop output, responsive to the second polarity edge of the system clock at the clock input.     
     
     
       5. The synchronizing circuit of claim 4, wherein: the second portion of combinatorial circuitry includes: N second portion combinatorial circuits, each combining a separate corresponding one of the N second polarity edge triggered flip flop outputs with the one of the N first polarity edge triggered flip flop outputs corresponding thereto;   a master combining circuit that combines together the outputs of the N second portion combinatorial circuits to generate the synchronizing circuit output signal.