Semiconductor device

Abstract

A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

What is claimed is: 
     
       1. A synchronous semiconductor memory device which inputs an address signal and control signals in synchronism with a clock signal, said synchronous semiconductor memory device comprising: a plurality of input circuits respectively having a differential amplifier circuit so that differential amplifier circuits of said input circuits are respectively provided with respect to the control signals other than a chip select and to each of bits of the address signal, each of said differential amplifier circuits being controlled to one of active and inactive states in response to an activation signal; and   an activation circuits coupled to said input circuits, outputting to said differential amplifier circuits the activation signal that undergoes a level change depending on a level change of said chip select signal and makes a transition to an active level when said chip select signal undergoes a transition to an active level.   
     
     
       2. The synchronous semiconductor memory device as claimed in claim 1, wherein said activation circuit comprises an inverter circuit inverting a signal output from one of said input circuits provided with respect to said chip select signal. 
     
     
       3. A synchronous semiconductor memory device which inputs an address signal and control signals in synchronism with a clock signal, said synchronous semiconductor memory device comprising: a plurality of input circuits respectively having a differential amplifier circuit so that differential amplifier circuits of said input circuits are respectively provided with respect to the control signals other than a chip select and to each of bits of the address signal, each of said differential amplifier circuits being controlled to one of active and inactive states in response to an activation signal; and   an activation circuit, coupled to said input circuits, outputting to said differential amplifier circuits the activation signal that undergoes a level change depending on a level change of said chip select signal and makes a transition to an active level when said chip select signal undergoes a transition to an active level or, outputting to said differential amplifier circuits the activation signal that has the active level.   
     
     
       4. The synchronous semiconductor memory device as claimed in claim 3, wherein said activation circuit comprises: an inverter circuit inverting a signal output from one of said input circuits provided with respect to said chip select signal;   a storage circuit having an output level thereof fixed to one of high and low levels in response to a predetermined command; and   a logic circuit obtaining a logical sum of outputs of said inverter circuit and said storage circuit, and outputting said activation signal.   
     
     
       5. The synchronous semiconductor memory device as claimed in claim 3, wherein said activation circuit comprises: an inverter circuit inverting a signal output from one of said input circuits provided with respect to said chip select signal;   a storage circuit having an output level thereof fixed to one of high and low levels; and   a logic circuit obtaining a logical sum of outputs of said inverter circuit and said storage circuit, and outputting said activation signal.   
     
     
       6. A synchronous semiconductor memory device which inputs an address signal and control signals in synchronism with a clock signal, said synchronous semiconductor memory device comprising: a plurality of input circuits respectively having a differential amplifier circuit so that differential amplifier circuits of said input circuits are respectively provided with respect to the control signals other than a chip select and to each of bits of the address signal, each of said differential amplifier circuits being controlled to one of active and inactive states in response to an activation signal; and   an activation circuit, coupled to said input circuits, outputting to said differential amplifier circuits the activation signal that undergoes a level change depending on a level change of said chip select signal and makes a transition to an active level when said chip select signal undergoes a transition to an active level until an active command instructing activation of a memory cell region is input,   said activation signal outputting to said differential amplifier circuits the activation signal having the active level until a precharge command instructing precharge of the memory region is input after said active command is input.   
     
     
       7. The synchronous semiconductor memory device as claimed in claim 6, wherein said activation circuit comprises: an inverter circuit inverting a signal output from one of said input circuits provided with respect to said chip select signal;   a storage circuit outputting a high-level signal until said precharge command is input after said active command is input and outputting a low-level signal until said active command is input after said precharge command is input; and   a logic circuit obtaining a logical sum of outputs of said inverter circuit and said storage circuit, and outputting said activation signal.   
     
     
       8. The synchronous semiconductor memory device as claimed in claim 6, wherein said activation circuit outputs the activation signal that makes a level change depending on a level change of said chip select signal when an operation of the synchronous semiconductor memory automatically changes to a precharge operation, and changes to the active level when said chip select signal changes to the active level. 
     
     
       9. The synchronous semiconductor memory device as claimed in claim 8, wherein said activation circuit comprises: an inverter circuit inverting a signal output from one of said input circuits provided with respect to said chip select signal;   a storage circuit outputting a high-level signal until said precharge command is input or until the operation of the synchronous semiconductor memory device automatically changes to the precharge operation after said active command is input, and outputting a low-level signal until said active command is input after said precharge command is input or after the operation automatically changes to the precharge operation; and   a logic circuit obtaining a logical sum of outputs of said inverter circuit and said storage circuit, and outputting said activation signal.