Polishing method for thin gates dielectric in semiconductor process

Abstract

A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600° C. to 900° C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide. In this embodiment, the deposited oxide is preferably fabricated by a chemical vapor deposition process using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300° C. to 600° C. and a pressure of less than approximately two torrs. In a presently preferred embodiment, the polishing includes depositing a slurry on a ceramic polishing pad and applying the gate dielectric to the polishing plate in the presence of the slurry while rotating the ceramic plate with respect to the semiconductor substrate. The slurry preferably comprises fumed silica suspended in a suspending solution. The suspending solution preferably comprises KOH or NH 3 OH. In one embodiment, the polishing plate is comprised of aluminum oxide.

What is claimed is: 
     
       1. A semiconductor process, comprising providing a semiconductor substrate   forming an initial gate dielectric layer on an upper surface of said semiconductor substrate;   polishing said initial gate dielectric layer with a chemical mechanical polish to produce a finished gate dielectric layer, wherein a thickness of said finished gate dielectric layer is less than a thickness of said initial gate dielectric layer and wherein said thickness of said finished gate dielectric layer is in the range of approximately 25 to 60 angstroms.   
     
     
       2. The process of claim 1, wherein the step of providing said semiconductor substrate comprises providing a monocrystalline silicon substrate, wherein said silicon substrate comprises a p-type epitaxial layer formed on a p+ silicon bulk, wherein a resistivity of said p-type epitaxial layer is in the range of approximately 10 to 15 Ω-cm and wherein a peak impurity concentration of said p+ silicon bulk is greater than approximately 10 19  atoms/cm 3 . 
     
     
       3. The process of claim 1, wherein the step of forming said initial gate dielectric layer comprises thermally oxidizing said semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 700 to 900° C. 
     
     
       4. The process of claim 1, wherein the step of forming said initial gate dielectric layer comprises depositing an oxide. 
     
     
       5. The process of claim 4, wherein said depositing comprises chemical vapor depositing said oxide using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300 to 600° C. and a pressure of less than approximately 2 torrs. 
     
     
       6. The process of claim 1, wherein said polishing comprises: depositing a slurry on a ceramic polishing plate; and   applying said initial gate dielectric layer to said polishing plate in the presence of said slurry while rotating said ceramic plate with respect to said semiconductor substrate.   
     
     
       7. The process of claim 6, wherein said slurry comprises fumed silica suspended in a suspending solution. 
     
     
       8. The process of claim 7, wherein said suspending solution comprises a material selected from the group consisting of KOH and NH 3  OH. 
     
     
       9. The process of claim 6, wherein said polishing plate comprises aluminum oxide. 
     
     
       10. A process for fabricating a dual gate dielectric thickness integrated circuit, comprising: providing a semiconductor substrate;   forming an initial gate dielectric layer on an upper surface of said semiconductor substrate, said initial gate dielectric layer having an initial thickness;   increasing a thickness of a first portion of said initial gate dielectric layer to a first thickness, wherein said first portion of said initial gate dielectric layer is aligned over a first region of said semiconductor substrate;   polishing said initial gate dielectric layer with a chemical mechanical polish to reduce said first thickness of said first portion to a final thickness, wherein said final thickness is less than said first thickness and greater than said initial thickness, wherein said initial gate dielectric layer comprises a first portion of said final thickness and a second portion of said initial thickness, said second portion aligned over a second region of said semiconductor substrate;   forming first and second conductive gate structures over said first and second portions respectively of said initial gate dielectric layer, wherein said conductive gate structures are aligned over respective channel regions within said first and second regions of said semiconductor substrate; and   forming first and second pairs of source/drain structures within first and second pairs of source/drain regions of said semiconductor substrate, wherein said pairs of source/drain regions are laterally displaced on either side of respective said channel regions of said semiconductor substrate.   
     
     
       11. The process of claim 10, wherein said semiconductor substrate, comprises a p-type epitaxial layer formed on a upper surface of an p+ silicon bulk, wherein a resistivity of said p-type epitaxial layer is in the range of approximately 10 to 15 Ω-cm. 
     
     
       12. The process of claim 10, wherein said semiconductor substrate comprises silicon and further wherein the step of forming said initial gate dielectric layer comprises immersing said semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 700 to 900° C. to thermally oxidize an upper surface of said semiconductor substrate. 
     
     
       13. The process of claim 10, wherein the step of increasing said thickness comprises selectively oxidizing a portion of said initial gate dielectric layer. 
     
     
       14. The process of claim 13, wherein the step of selectively oxidizing said portion comprises: forming an oxidation inhibiting mask over said second portion of said initial gate dielectric layer; and   immersing said semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 700 to 900° C.   
     
     
       15. The process of claim 14, wherein said oxidation inhibiting mask comprises silicon nitride. 
     
     
       16. The process of claim 10, wherein said polishing comprises: depositing a slurry on a ceramic polishing plate; and   applying said initial gate dielectric layer to said polishing plate in the presence of said slurry while rotating said polishing plate with respect to said semiconductor substrate.   
     
     
       17. The process of claim 16, wherein said slurry comprises fumed silica suspended in a suspending solution. 
     
     
       18. The process of claim 17, wherein said suspending solution is selected from the group consisting of KOH and NH 3  OH. 
     
     
       19. The process of claim 16, wherein said polishing plate comprises aluminum oxide.