Translating SCSI bus control and/or data signals between differential and single-ended formats

Abstract

An apparatus is disclosed for translating between differential and single-ended SCSI signals. The apparatus includes programmable array logic. The TTL equivalent of both differential and single-ended control signals can be inputted to the PAL. The outputs of the PAL are used, together with control logic gates, in controlling the direction of transmission of SCSI control signals. In one embodiment, only bi-directional SCSI control signals are inputted to the PAL. In another embodiment, all SCSI control signals are inputted thereto. In one embodiment, terminator power is used to power components of the translating apparatus.

What is claimed is: 
     
       1. An apparatus for translating SCSI control signals, comprising: first means for receiving a first plurality of control signals from a single-ended SCSI bus;   second means for receiving a second plurality of control signals from a differential SCSI bus, wherein one of said first plurality and second plurality of control signals being outputted by a target device and the other thereof being outputted by an initiator device, said first plurality of control signals having a first subgroup and said second plurality of control signals having a second subgroup, wherein each of said control signals in said first subgroup has a counterpart signal in said second subgroup having the same function, and in which each of said control signals in said first subgroup and its counterpart in said second subgroup is defined as a counterpart pair and said control signals of said counterpart pair represent bidirectional SCSI signals, with one of said counterpart pairs representing bidirectional reset signals including a single-ended reset signal and a differential reset signal; and   third means responsive to said first and second means for controlling transmission of said counterpart pairs through said apparatus, said third means including programmable array logic and control logic circuitry communicating with said programmable array logic, said programmable array logic including input lines for inputting said counterpart pairs and output lines for outputting two enable signals for each of said counterpart pairs, said control logic circuitry having input lines for inputting said counterpart pairs and being responsive to said enable signals and transmitting or blocking said signals in said counterpart pair in response to said enable signals.   
     
     
       2. An apparatus, as claimed in claim 1, wherein: said first subgroup includes said single-ended reset, single-ended select and single-ended busy signals and said second subgroup includes said differential reset, differential select and differential busy signals.   
     
     
       3. An apparatus, as claimed in claim 2, wherein: each of said enable signals has a logic state and said logic state of a first of said enable signals depends substantially only on said single-ended reset and said differential reset, said logic state of a second of said enable signals depends substantially only on said single-ended select and said differential select and said logic state of a third of said enable signals depends substantially only on said single-ended busy and said differential busy.   
     
     
       4. An apparatus, as claimed in claim 1, wherein: said two enable signals of each of said counterpart pairs have opposite logic states.   
     
     
       5. An apparatus, as claimed in claim 1, wherein: at least each of three enable signals of said counterpart pairs being generated using logic that is substantially the same but comprised of different logic means in said programmable array logic.   
     
     
       6. An apparatus, as claimed in claim 1, wherein: said programmable array logic generates a priority signal that depends upon a control signal from the single-ended SCSI bus and said counterpart control signal from the differential SCSI bus.   
     
     
       7. An apparatus, as claimed in claim 6, wherein: a logic state of said first priority signal depends substantially only upon said single-ended reset and said differential reset.   
     
     
       8. An apparatus, as claimed in claim 1, wherein: said counterpart pairs include single-ended select and a differential select and a single-ended busy and differential busy signals and in which a combination of said single-ended reset and said differential reset is applied to logic that is substantially equivalent to that logic to which each of a combination of said single-ended select and said differential select is applied and a combination of said single-ended busy and said differential busy is applied.   
     
     
       9. An apparatus, as claimed in claim 1, wherein: said first means includes first connecting means and said second means includes second connecting means, wherein the single-ended SCSI bus is connectable to one of said first and second connecting means and the differential SCSI bus is connectable to the other one of said first and second connecting means and in which the initiator device is selectably connectable to either one of the single-ended and differential busses.   
     
     
       10. An apparatus, as claimed in claim 1, wherein: said control logic gate circuitry includes a plurality of control gates, each of said control gates for receiving a predetermined control signal of said counterpart pairs, each of said control gates being controlled using one of said enable signals from said programmable array logic.   
     
     
       11. An apparatus, as claimed in claim 1, further including: first terminator power means in the single-ended SCSI bus for supplying power to components of at least one of said first means, second means and third means.   
     
     
       12. An apparatus, as claimed in claim 11, wherein: said first terminator power means includes a first terminator power pin receiving power from a SCSI device.   
     
     
       13. An apparatus, as claimed in claim 1, wherein: at least two target devices are connected to the single-ended SCSI bus and at least a first initiator device and one of a second initiator device and a target device are connected to the second differential SCSI bus, wherein terminating means is connected to each end of the single-ended and differential SCSI busses and each of the initiator and target devices is also connected to each of the ends.   
     
     
       14. A method for translating between SCSI single-ended and differential signals using single-ended and differential SCSI busses and in which a target device and an initiator device communicate with a different one of each of the two busses, comprising: receiving by said differential SCSI bus at controlled times each one of a plurality of first SCSI control signals communicating with said target device, said first SCSI control signals including at least differential reset, differential select and differential busy;   receiving by said single-ended SCSI bus at controlled times each one of a plurality of second SCSI control signals communicating with said initiator device, said second SCSI control signals including at least single-ended reset, single-ended select and single-ended busy, said differential reset and single-ended reset signals defining a counterpart pair, said differential select and single-ended select signals defining a counterpart pair and said differential busy and single-ended busy signals defining a counterpart pair; and   controlling transferring data and control signals between differential and single-ended SCSI busses, wherein said controlling step includes determining, for each of said counterpart pairs, whether to transmit one thereof and in which, for each of said counterpart pairs, said determining step is conducted independently of said other counterpart pairs including determining whether to transmit one of said differential reset and single-ended reset signals independently of said signals of said other counterpart pairs.   
     
     
       15. A method, as claimed in claim 14, wherein: said controlling step includes using programmable array logic and said determining step includes using substantially the same logic but different logic means in said programmable array logic in determining whether to transmit one of said counterpart pairs for each of said counterpart pairs.   
     
     
       16. A method, as claimed in claim 14, wherein: said controlling step includes regulating first and second control gates using enable signals.   
     
     
       17. A method, as claimed in claim 14, wherein: said controlling step includes using programmable array logic and said step of determining includes ascertaining whether one of a single-ended busy signal and a differential busy signal is present using said programmable array logic wherein said presence is determined using substantially only said single-ended busy and differential busy signals.   
     
     
       18. A method, as claimed in claim 17, wherein: said controlling step includes generating a differential busy priority signal when said differential busy signal and said single-ended busy signal are received at the same time by said programmable array logic.   
     
     
       19. A method, as claimed in claim 14, further including: supplying power using first terminator power means to components used in said method and which components are connected to at least one of said differential and single-ended SCSI busses.   
     
     
       20. An apparatus, as claimed in claim 1, where: said programmable array logic generates an enable signal for each counterpart pair independently of said other counterpart pairs including generating enable signals for said differential reset and single-ended reset signals independently of said other counterpart pairs.