High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom

Abstract

This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings. And, The memory cell further includes a patterned third polysilicon layer overlying the second TEOS oxide layer and in contact with the silicide for contacting the connector thereunder wherein the patterned third polysilicon layer containing dopants therein to function as a load resistor for the memory cell.

I claim: 
     
       1. A memory cell having a first polysilicon as a gate comprising: a first TEOS oxide layer overlying said first polysilicon and a plurality of via-1 openings exposing said first polysilicon therein;   a patterned second polysilicon layer overlying said first TEOS oxide layer and filling said via-1 openings thus contacting said gate wherein said patterned second polysilicon containing dopant ions for functioning as a connector for said memory cell;   a second TEOS oxide layer overlying said connector includes a plurality of via-2 openings for exposing said connector therein;   a silicide barrier layer disposed in said via-2 openings; and   a patterned third polysilicon layer overlying said second TEOS oxide layer and in contact with said silicide for contacting said connector thereunder wherein said patterned third polysilicon layer containing dopants therein to function as a load resistor for said memory cell.   
     
     
       2. The memory cell of claim 1 wherein: said silicide barrier layer containing materials formed with Ti/TiN and tungsten annealed at an elevated temperature.   
     
     
       3. The memory cell of claim 1 wherein: said memory cell having a cell size ranging from 0.2 to 1.0 micrometer and said connector having a length ranging from 0.2 to 0.8 micrometer and said load resistor having a length ranging from 0.2 to 0.8 micrometer having a resistivity greater than a resistivity of said connector.   
     
     
       4. A memory cell comprising: a patterned polysilicon layer in electrical contact with a gate of said memory cell functioning as a connector;   a barrier layer overlying said connector;   a patterned second polysilicon layer above said barrier layer functioning as a load resistor; and   said barrier layer including a silicide barrier disposed in a plurality via openings in an insulation layer overlying said connector.