Double damascene pattering of silcon-on-insulator transistors

Abstract

The present invention is a technique for producing silicon-on-insulator MOS transistors by damascene patterning of source-drain regions in a thin film of amorphous silicon deposited on a layer of oxide grown on a silicon wafer, where the oxide has previously been etched with a pattern of trenches. In addition, the technique provides for the amorphous layer to contact the underlying silicon substrate through multiple small oxide openings; where these openings have been previously filled with amorphous silicon, planarized and annealed at high temperature to form single crystal silicon; and where subsequent transistor channel regions will align to these filled openings. After patterning, the wafer is annealed in a second high temperature cycle, where the regions of amorphous silicon in contact with the single crystal silicon in the openings will convert into single crystal silicon suitable for transistor channel regions.

I claim: 
     
       1. A silicon-on-insulator (SOI) substrate process where a first insulating layer is grown or deposited onto a silicon wafer; where one or more first openings are etched to the silicon wafer through this first layer, with the openings positioned to align to subsequent MOS transistor channel regions;   where a first layer of amorphous silicon is deposited thicker than the first insulating layer thickness;   where this first amorphous silicon layer is chemically-mechanically polished leaving only amorphous silicon in the first openings, with the top surface of the amorphous silicon becoming flush with the top surface of the first insulating layer;   where the wafer is annealed to a high enough temperature to convert the first amorphous silicon into single crystal silicon;   where next a thin layer of an etch stop material is deposited and a second insulating layer is deposited;   where the second insulating layer is etched with a second pattern of openings, stopping at the etch stop, and continuing to etch the etch stop, stopping at the underlying first insulating layer or at the underlying silicon in the first openings;   where these second openings are the shape of, and laterally positioned to where a subsequent MOS transistor's source, drain and channel areas will be positioned;   where the first openings will be laterally positioned within the second openings, and beneath the channel regions of subsequent MOS transistors;   where a second layer of amorphous silicon is deposited to a thickness greater than the thickness of the second insulating layer;   where the second amorphous silicon layer is chemically-mechanically polished leaving only silicon in the first openings, whose top surface is flush with the top surface of the second insulating layer;   where the wafer is annealed to a high enough temperature to convert to single crystal those regions of the second amorphous layer that are directly over the single crystal silicon in the first openings.   
     
     
       2. The process of claim 1, where the insulating layers are silicon dioxide. 
     
     
       3. The process of claim 1, where the first insulating layer is approximately 2000 Å thick, and the second insulating layer is approximately 1000 Å thick. 
     
     
       4. The process of claim 1, where the etch stop layer is silicon nitride. 
     
     
       5. The process of claim 4, where the silicon nitride is approximately 100 Å thick. 
     
     
       6. The process of claim 5, where the single crystal silicon in the first openings has a thin film of oxide grown just prior to the etch stop deposition.