Thin-film transistor and SRAM memory cell equipped therewith

Abstract

A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region. The channel region is formed to be adjacent to the source region and the first drain region. The first drain region is formed to be adjacent to the channel region and the second drain region.

What is claimed is: 
     
       1. A thin-film transistor comprising: a substrate;   a patterned semiconductor film formed on a main surface of said substrate;   at least the main surface of said substrate having an insulating property;   said patterned semiconductor film being made of a silicon-system semiconductor material and being not monocrystalline;   said patterned semiconductor film including a source region of a first conductivity type, a channel region of a second conductivity type opposite to said first conductivity type, a first drain region of said first conductivity type, and a second drain region of said second conductivity type;   said first drain region serving as an offset region;   a gate electrode formed to be opposite to said channel region through a gate insulating film;   said source region being formed on one end of said semiconductor film;   said second drain region being formed on an opposite end of said semiconductor film to said source region;   said channel region being formed to be adjacent to said source region and said first drain region;   said first drain region being formed to be adjacent to said channel region and said second drain region;   a first voltage being applied across said source region and said second drain region;   a second voltage being applied to said gate electrode.   
     
     
       2. A transistor as claimed in claim 1, wherein said channel region has a doping concentration less than that of said first drain region. 
     
     
       3. A transistor as claimed in claim 1, wherein said gate electrode is located on an opposite side to said substrate with respect to said gate insulating film. 
     
     
       4. A transistor as claimed in claim 1, wherein said gate electrode is located on a same side as said substrate with respect to said gate insulating film.