Precision capacitor ladder using differential equal-perimeter pairs

Abstract

An integrated circuit capacitor ladder which uses a differential pair of capacitors for each step in the ladder. By pairing a square with a rectangle of equal perimeter, the contributions of edge and corner elements can be canceled out. This adds area and complexity, but greatly increases the precision of scaling.

What is claimed is: 
     
       1. An integrated circuit capacitor structure, comprising: first and second arrays of capacitors, connected to receive identical selection inputs and to selectively connect and disconnect capacitors accordingly;   wherein individual capacitors of said first array each have a perimeter which is equal to that of a corresponding capacitor in said second array, and an area which differs from that of said corresponding capacitor by a desired differential capacitance value; and   means for receiving a first output from said first array and a second output from said second array, and for performing a subtraction operation thereon to simulate an ideal capacitor which has a value equal to one of said differential capacitance values;   whereby the contributions of edge and corner elements of said individual capacitors of said first and second arrays are canceled out by said subtraction operation.   
     
     
       2. The integrated circuit structure of claim 1 wherein each said capacitor is a MOS capacitor. 
     
     
       3. The integrated circuit structure of claim 1 wherein said means is combined with said first array. 
     
     
       4. The integrated circuit structure of claim 1 wherein some ones of said individual capacitors are each implemented as a pair of capacitors in parallel. 
     
     
       5. The integrated circuit structure of claim 1 wherein said selection input is a binary signal which includes at least six bits. 
     
     
       6. An integrated circuit capacitor structure, comprising: first and second arrays of capacitors, connected to receive an identical signal input, and connected to receive identical selection inputs and to selectively connect and disconnect capacitors from said signal input accordingly;   wherein individual capacitors of said first array each have a perimeter which is equal to that of a corresponding capacitor in said second array, and an area which differs from that of said corresponding capacitor by a respective differential capacitance value;   and wherein corresponding ones of said capacitors of said first and second arrays have areas such that said differential capacitance values are scaled in a fixed dependence on said selection inputs; and   a differential processing stage connected to receive signal outputs from said first and second arrays, and to perform a subtraction operation thereon to simulate an ideal capacitor, controlled by said selection input, which has a value equal to said respective differential capacitance value;   whereby the contributions of edge and comer elements of said individual capacitors of said first and second arrays are canceled out by said subtraction operation.   
     
     
       7. The integrated circuit structure of claim 6 wherein each said capacitor is a MOS capacitor. 
     
     
       8. The integrated circuit structure of claim 6 wherein some ones of said individual capacitors are each implemented as a pair of capacitors in parallel. 
     
     
       9. The integrated circuit structure of claim 6 wherein said selection input is a binary signal which includes at least six bits. 
     
     
       10. An integrated circuit capacitor structure, comprising: first and second arrays of capacitors, both connected to receive a common signal input from a common input switch, and each connected to provide a respective output signal input through a respective output switch, and both connected to receive a common n-bit selection input and to selectively connect and disconnect capacitors from said signal input accordingly;   wherein individual capacitors of said first array each have a perimeter which is equal to that of a respective corresponding capacitor at a corresponding bit position in said second array, and an area which differs from that of said corresponding capacitor by a respective differential capacitance value;   and wherein corresponding ones of said capacitors of said first and second arrays have areas such that said differential capacitance values are scaled in powers of two; and   a differential processing stage connected to receive signal outputs from said respective output switches of first and second arrays, and to perform a subtraction operation thereon to simulate an ideal capacitor, controlled by said selection input, which has a value equal to said respective differential capacitance value;   whereby the contributions of edge and comer elements of said individual capacitors of said first and second arrays are canceled out by said subtraction operation.   
     
     
       11. The integrated circuit structure of claim 10 wherein each said capacitor is a MOS capacitor. 
     
     
       12. The integrated circuit structure of claim 10 wherein some ones of said individual capacitors are each implemented as a pair of capacitors in parallel. 
     
     
       13. The integrated circuit structure of claim 10 wherein said selection input is a binary signal which includes at least six bits. 
     
     
       14. An integrated circuit capacitor array structure, comprising: a first array of capacitors including a number of individual integrated circuit capacitors, each individual integrated circuit capacitor having regions formed to have a substantially predetermined area and perimeter;   a second array of capacitors including a number of individual integrated circuit capacitors, each individual integrated circuit capacitor having regions formed to have a substantially predetermined area and perimeter, and each capacitor of the second array being associated with a capacitor in the first array by having the same perimeter and an area differing by a predetermined amount from its associated capacitor in the first array; and   a control circuit coupled to the first and second arrays of capacitors operable to select ones of the capacitors in the first array and the respective associated capacitors in the second array and develop on an output terminal a value dependent on the difference between the capacitance values of the selected capacitors.   
     
     
       15. The integrated circuit capacitor array structure of claim 14 wherein each of capacitors in the first array has rectangular shaped regions having the predetermined area and perimeter. 
     
     
       16. The integrated circuit capacitor array structure of claim 14 wherein each of capacitors in the second array has a rectangular shaped regions having the predetermined area and perimeter. 
     
     
       17. The integrated circuit capacitor array structure of claim 14 wherein each of the capacitors in the first and second arrays is formed by electrically interconnecting a plurality of individual capacitive elements, each individual capacitive element including a square region formed with sides having a minimum length. 
     
     
       18. A method of fabricating an integrated circuit capacitor array structure, the method comprising the steps of: forming a plurality of integrated circuit capacitors, each integrated circuit capacitor having regions of a predetermined area and perimeter, the capacitors being formed so that there are pairs of capacitors having equal perimeters and areas that differ by a predetermined amount;   selecting at least a pair of integrated circuit capacitors; and   using the difference between the capacitance values of the selected pair of capacitors to operate on an input signal and provide an output signal having a value dependent on this difference.   
     
     
       19. The method of claim 18 wherein each of the regions has a rectangular shape.