Non-volatile semiconductor memory device

Abstract

A non-volatile semiconductor memory device includes a first memory cell array, a second memory cell array that can be accessed by an address identical to that for the first memory cell array, and a decision circuit which executes an operation on data stored in the first and second memory cell arrays and a predetermined fixed value, a result of the given operation being output data to be externally output.

What is claimed is: 
     
       1. A non-volatile semiconductor memory device comprising: a first memory cell array;   a second memory cell array that can be accessed by an address identical to that for the first memory cell array; and   a decision circuit which executes an operation on data stored in the first and second memory cell arrays and a predetermined fixed value, a result of the operation being output data to be externally output.   
     
     
       2. The non-volatile semiconductor memory device as claimed in claim 1, wherein: the fixed value is set equal to a first data value which may mistakenly be changed to a second data value with a possibility higher than the second data value may be changed to the first data value; and   the decision circuit makes a majority decision on the data stored in the first and second memory cell arrays and the fixed value, so that an error in which the first data value is changed to the second data value can be corrected.   
     
     
       3. The non-volatile semiconductor memory device as claimed in claim 2, further comprising: a failure address memory circuit which stores an address of a defective memory cell transistor which is located in one of the first and second memory cell arrays; and   a compare circuit which compares the address stored in the failure address memory circuit with the address externally supplied and determines whether both addresses coincide with each other,   the decision circuit changing the fixed value from the first data value to the second data value if the compare circuit determines that both the addresses coincide with each other.   
     
     
       4. The non-volatile semiconductor memory device as claimed in claim 1, wherein: the data stored in the first and second memory cell arrays is arranged so as to have performance so that a first data value may mistakenly be changed to a second data value with a possibility higher than the second data value may be changed to the first data value;   the fixed value is set equal to the first data value; and   the decision circuit makes a majority decision on the data stored in the first and second memory cell arrays and the fixed value, so that an error in which the first data value is changed to the second data value can be corrected.   
     
     
       5. The non-volatile semiconductor memory device as claimed in claim 4, further comprising: a failure address memory circuit which stores an address of a defective memory cell transistor which is located in one of the first and second memory cell arrays; and   a compare circuit which compares the address stored in the failure address memory circuit with the address externally supplied and determines whether both addresses coincide with each other,   the decision circuit changing the fixed value from the first data value to the second data value if the compare circuit determines that both the addresses coincide with each other.   
     
     
       6. The non-volatile semiconductor memory device as claimed in claim 1, further comprising: a failure address memory circuit which stores an address of a defective memory cell transistor which is located in one of the first and second memory cell arrays; and   a compare circuit which compares the address stored in the failure address memory circuit with the address externally supplied and determines whether both addresses coincide with each other,   the decision circuit changing the fixed value to another fixed value if the compare circuit determines that both the addresses coincide with each other.   
     
     
       7. A non-volatile semiconductor memory device comprising: a first memory cell array;   a second memory cell array that can be accessed by an address identical to that for the first memory cell array; and   a logic gate which executes a logic operation on data stored in the first and second memory cell arrays,   wherein the data stored in the first and second memory cell arrays is arranged so as to have performance so that a first data value may mistakenly be changed to a second data value with a possibility higher than the second data value may be changed to the first data value, a result of the logic operation being output data to be externally output.   
     
     
       8. The non-volatile semiconductor memory device as claimed in claim 7, wherein the logic gate is an OR gate. 
     
     
       9. The non-volatile semiconductor memory device as claimed in claim 7, wherein the logic gate is an AND gate. 
     
     
       10. The non-volatile semiconductor memory device as claimed in claim 7, wherein the logic gate comprises: an OR gate performing an OR operation on the data stored in the first and second memory cell arrays;   an AND gate performing an AND operation on the data stored in the first and second memory cell arrays; and   a selector which selects one of results of the OR and AND gates, a selected result being output data to be externally output.