Method and apparatus for duty-cycle correction

Abstract

Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.

What is claimed is: 
     
       1. A duty-cycle corrector, comprising: a clipper receiving an input signal having first rising edges and first falling edges;   a duty-cycle detector coupled to the clipper, the duty-cycle detector detecting a duty-cycle of an output signal of the clipper and generating an offset signal based on the duty-cycle, wherein the duty-cycle is changed by changing positions of zero crossings along the first rising and the first falling edges said slew-rate limiter comprising a differential circuit, of the input signal based on the offset signal; and   a slew-rate limiter coupled to the clipper, said slew-rate limiter receiving an external signal having second rising edges and second falling edges and generating the input signal having the first rising edges and first falling edges, wherein the slew-rate limiter limits slew rates of the first rising edges and first falling edges of the iniput signal based on the second rising edges and the second falling edges of the external signal.   
     
     
       2. The duty-cycle corrector of claim 1, wherein each of the first rising edges has a first slope in an amplitude-time plane and each of the first falling edges has a second slope in the amplitude-time plane, the positions of the zero crossings along an amplitude axis of the first rising and the first falling edges being changed according to the offset signal resulting in a change of time between adjacent zero crossings determined by the first and the second slopes. 
     
     
       3. The duty-cycle corrector of claim 2, wherein the slew-rate limiter comprises: a first pair of transistors generating the first rising and the first falling edges; and   a first resistor-capacitor pair coupled to a first transistor of the first pair of transistors and a second resistor-capacitor pair coupled to a second transistor of the first pair of transistors first and the second resistor-capacitor pairs limit the slew-rates of the first rising and the first failings edges.   
     
     
       4. The duty-cycle corrector of claim 1, wherein the clipper generates the clipper output signal by amplifying the input signal and limiting an amplitude of the clipper output signal to be between a maximum value and a minimum value. 
     
     
       5. The duty-cycle corrector of claim 1, wherein rising edges and falling edges of the clipper output signal correspond to positions of the zero crossings of the clipper input signal along a time axis. 
     
     
       6. The duty-cycle corrector of claim 4, wherein rising edges and falling edges of the clipper output signal correspond to positions of the zero crossings of the clipper input signal along a time axis. 
     
     
       7. The duty-cycle corrector of claim 4, wherein the clipper comprises: a second pair of transistors amplifying the input signal;   a pair of resistors coupled to the second pair of transistors; and   a third pair of transistors coupled to the second pair of transistors and configured as emitter followers, the third pair of transistors generating the clipper output signal based on an output of the second pair of transistors.   
     
     
       8. The duty-cycle corrector of claim 4, wherein the duty-cycle detector comprises: an integrator receiving the clipper output signal, the integrator integrating the clipper output signal to generate an integrator output signal that corresponds to the duty-cycle of the clipper output signal; and   an amplifier that receives and amplifies the integrator output signal to generate the offset signal.   
     
     
       9. The duty-cycle corrector of claim 8, wherein the integrator comprises: a fourth pair of transistors having integrator input terminals that receive the clipper output signal and integrator output terminals that output an integrator output signal;   an integrator biasing circuit coupled to the integrator output terminals; and   an integrator capacitor coupled to the integrator biasing circuit and the integrator output terminals, the integrator capacitor integrating the clipper output signal to produce the integrator output signal that reflects the duty-cycle of the clipper output signal.   
     
     
       10. The duty-cycle corrector of claim 8, wherein the integrator comprises: a fourth pair of transistors having integrator input terminals that receive the clipper output signal and integrator output terminals that output the integrator output signal;   an integrator biasing circuit coupled to the integrator output terminals; and   an integrator capacitor coupled to the integrator biasing circuit and the integrator output terminals, the integrator capacitor integrating the clipper output signal to produce the integrator output signal that reflects the duty-cycle of the clipper output signal.   
     
     
       11. The duty-cycle corrector of claim 8, wherein the amplifier comprises: a first stage amplifier coupled to the integrator that amplifies the integrator output signal; and   a second stage amplifier coupled to the first stage amplifier, the second stage amplifier converting an output signal of the first stage amplifier into a current output representing the offset signal and outputting the offset signal.   
     
     
       12. The duty-cycle corrector of claim 11, wherein the first stage amplifier comprises: a fifth pair of transistors receiving the integrator output signal through first stage input terminals, the fifth pair of transistors amplifying the integrator output signal to generate a first stage output signal at first stage output terminals; and   a first stage biasing circuit that includes a biasing transistor, two resistors and a capacitor, the capacitor sets a bandwidth of the first stage amplifier that reduces a ripple in the first stage output signal at a frequency of the input signal.   
     
     
       13. The duty-cycle corrector of claim 11, wherein the second stage amplifier comprises a sixth pair of transistors coupled to the first stage output terminals, the sixth pair of transistors converting the first stage output signals into the offset signal. 
     
     
       14. A method for correcting a duty-cycle, comprising: receiving an input signal having first rising edges and first falling edges in a clipper;   receiving an external signal having second rising and second falling edges;   limiting slew rates of the first rising edges and the first falling edges of the input signal using a slew-rate limiter, the comprises a differential circuit the frequency of the input signal being based on the frequency of the external signal;   detecting a duty-cycle of an output signal of the clipper;   generating an offset signal based on the duty-cycle; and   changing positions of zero crossings along the first rising and the first falling edges of the input signal based on the offset signal to change the duty-cycle signal.   
     
     
       15. The method of claim 14, wherein each of the first rising edges has a first slope in an amplitude-time plane and each of the first falling edges has a second slope in the amplitude-time plane, the positions of the zero crossings along an amplitude axis of the first rising and the first falling edges being changed according to the offset signal resulting in a change of time between adjacent zero crossings determined by the first and the second slopes. 
     
     
       16. The method of claim 14, wherein the clipper generates the output signal by amplifying the input signal and limiting an amplitude of the clipper output signal to be between a maximum value and a minimum value. 
     
     
       17. The method of claim 15, wherein rising edges and falling edges of the clipper output signal correspond to positions of the zero crossings of the input signal along a time axis. 
     
     
       18. The duty-cycle corrector of claim 3, wherein the first pair of transistors are bipolar transistors. 
     
     
       19. The duty-cycle corrector of claim 7, wherein the second pair of transistors and the third pair of transistors are bipolar transistors. 
     
     
       20. The duty-cycle corrector of claim 10, wherein the fourth pair of transistors are bipolar transistors and said integrator biasing circuit comprises a pair of p-channel devices, two resistors and two capacitors. 
     
     
       21. The duty-cycle corrector of claim 12, wherein the fifth pair of transistors are bipolar transistors. 
     
     
       22. The duty-cycle corrector of claim 13, wherein the sixth pair of transistors are bipolar transistors.