US5942782AExpiredUtility

Electrostatic protection component

Assignee: UNITED MICROELECTRONICS CORPPriority: May 21, 1997Filed: Sep 17, 1997Granted: Aug 24, 1999
Est. expiryMay 21, 2017(expired)· nominal 20-yr term from priority
Inventors:Chen-Chung Hsu
H10D 89/811H10D 84/0142H10D 84/0137H10D 84/038H10D 84/013
32
PatentIndex Score
1
Cited by
0
References
7
Claims

Abstract

An electrostatic protection component and a method for forming the same. The method includes forming a gate consisting of a gate oxide layer and a conducting layer above a semiconductor substrate. Spacers are formed on the peripheral sidewalls of the gate. First heavily doped regions are formed in the semiconductor substrate. A metallic layer is formed covering the semiconductor substrate followed by a heating process. First metal silicide layers are formed above the gate while second metal silicide layers are formed above the first heavily doped regions. A photoresist layer is coated above the semiconductor substrate, exposing the first metal silicide layer and part of the second metal silicide layer adjacent to each side of the gate. An etching operation removes the spacers and part of the conducting layer to expose part of the gate oxide layer surface, so that the gate is ultimately transformed into an I-shaped structure having an upper first metal silicide layer, a middle conducting layer and a lower gate oxide layer. An insulating layer is formed above the semiconductor substrate. Contact window openings are formed in the insulating layer exposing the second metal silicide layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An electrostatic protection component formed on a semiconductor substrate comprising: a transistor formed above the semiconductor substrate for collecting an electrostatic discharging current, having gate and source/drain regions, the gate region defining an I-shaped structure having an upper first metal silicide layer, a middle conducting layer, and a lower oxide layer, each source/drain region having a first heavily doped region located below a periphery of the lower oxide layer, the first heavily doped region being connected to a periphery of a second heavily doped region, and a second metal silicide layer formed above the first heavily doped region; and   an insulating layer with a plurality of contact window openings exposing the second metal silicide layer.   
     
     
       2. A component according to claim 1, wherein a distance from the conducting layer to the nearest contact window opening is about 3 μm to 4 μm. 
     
     
       3. A component according to claim 1, wherein a width of the first metal silicide layer is between about 5 μm to 7 μm. 
     
     
       4. A component according to claim 1, wherein the conducting layer includes a polysilicon layer. 
     
     
       5. A component according to claim 1, wherein a width of the conducting layer is about 1 μm. 
     
     
       6. A component according to claim 1, wherein the first heavily doped region includes implanted arsenic ions. 
     
     
       7. A component according to claim 1, wherein the second heavily doped region includes implanted arsenic ions.

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