Simulation method and simulation system

Abstract

At least two test instructions are sequentially simulated. Concurrently the number of clocks taken for simulating at least two test instructions are counted. The peripheral processing program relating to at least two test instructions are simulated for the number of clocks counted after simulating at least two test instructions.

What is claimed is: 
     
       1. A simulation method comprising the steps of: simulating at least two test instructions sequentially;   counting a respective number of clock cycles taken for simulating each of said at least two test instructions; and then   simulating a peripheral processing program relating to said at least two test instructions for a total number of clock cycles taken for said at least two test instructions;   detecting an interruption during simulation of said peripheral processing program; then   sequentially simulating at least two interruption processing instructions relating to said interruption;   counting a number of clock cycles taken for simulating said at least two interruption processing instructions;   adding up said number of clock cycles taken for simulating said at least two interruption processing instructions to provide a total interruption clock cycles number;   storing said total interruption clock cycles number; and then   simulating said peripheral processing program relating to said at least two interruption processing instructions for said total interruption clock cycles number.   
     
     
       2. A simulation method comprising steps of: simulating a test instruction and counting the number of clock cycles for simulating said test instruction; then   adding up counted numbers of clock cycles sequentially and storing the number of clock cycles taken for executing at least two test instructions;   counting the number of executed test instructions;   judging whether a predetermined test instruction has been simulated; and   simulating a peripheral processing program relating to said at least two test instructions for the number of clock cycles stored in said memory step upon the occurrence of the earlier of: said judgment indicating that predetermined test instruction has been simulated, and   said number of executed test instructions reaching a predetermined value;     simulating an interruption processing instruction after completing simulation of said peripheral processing program and counting the number of clock cycles taken for simulating said interruption processing instruction in case an interruption occurs during simulation of said peripheral processing program;   adding up counted numbers of clock cycles sequentially and storing the number of clock cycles required for executing at least two test instructions; and   simulating said peripheral processing program relating to said at least two interruption processing instructions for the number of clock cycles stored in said memory step after simulating said at least two interruption processing.   
     
     
       3. A simulation system comprising: test instruction simulation means for simulating at least two test instructions sequentially and counting the number of clock cycles taken for simulating said at least two test instructions; and   peripheral processing program simulation means for simulating a peripheral processing program relating to said at least two instructions for the number of clock cycles counted by said test instruction simulation means after simulating said at least two instructions;   interruption processing simulation means for sequentially simulating at least two interruption processing instructions in synchronization with clock signals and for counting the number of clock cycles taken for simulating said at least two interruption processing instructions;   means for simulating said peripheral processing program, relating to said at least two interruption processing instructions, for the number of clock cycles counted by said interruption processing instruction simulation means and for and simulating said peripheral processing program when an interruption occurs during simulation of said peripheral processing program; and   means for controlling respective values of a program status word and a program counter.   
     
     
       4. A simulation system comprising: file input means for inputting a test program;   program storing means for storing an input test program;   read means for reading said test program from said program storing section;   analysis means for analyzing a test instruction intended for simulation based on said test program which has been read;   simulating means for simulating the test instruction analyzed by said analysis means synchronized with clock signals;   storing means for counting the numbers of clock cycles required for simulating said test instructions sequentially and storing the number of clock cycles taken for simulating at least two test instructions;   count means for counting the number of simulated test instructions; and   simulating means for simulating a peripheral processing program for the number of clock cycles stored in said storing means in case the number of count of said count means reaches a predetermined value or a predetermined test instruction has been simulated;   interruption processing instruction simulation means for sequentially simulating at least two interruption processing instructions in synchronization with clock signals and for counting the number of clock cycles taken for simulating said at least two interruption processing instructions;   means for collectively simulating said peripheral processing program relating to said at least two interruption processing instructions once for the number of clock cycles counted by said interruption processing instruction simulation means; and   means for controlling respective values of a program status word and a program counter.